FPGA Development Lead (level 4)

Firefly Aerospace•Cedar Park, TX

About The Position

The FPGA Development Lead is a senior technical leader and hands-on contributor responsible for designing, implementing, and verifying high-reliability FPGA designs for launch vehicles, spacecraft, and ground systems. The role provides technical direction and mentorship to FPGA engineers, drives development best practices, and contributes directly to RTL design, verification, timing closure, and hardware integration. The lead partners with embedded software, hardware, GNC, systems engineering, and other stakeholders to deliver reliable FPGA solutions and continually improve development practices. The position is suited to someone comfortable with a fast-paced startup environment, changing needs, technical ownership, creativity, flexibility, and multidisciplinary collaboration.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 8 years of FPGA development experience.
Strong proficiency in VHDL and/or Verilog/SystemVerilog for RTL design.
Experience with FPGA architectures such as AMD/Xilinx, Intel/Altera, or similar, including timing closure, place-and-route, and constraints.
Hands-on experience with FPGA lab bring-up, debugging, and integration with embedded systems or hardware.
Demonstrated ability to mentor or technically lead engineers; formal people management is not required.
Ability to work in a dynamic environment with changing needs and requirements.
Team-oriented, can-do attitude, and comfort contributing independently and collaboratively.
Willingness to take on challenges and learn new skills.
Excellent written and verbal communication skills.
Must be a U.S. citizen, lawful permanent resident, protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain required U.S. Department of State authorizations for compliance with U.S. Government space technology export regulations, including ITAR.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience with high-speed interfaces such as SERDES, PCIe, Ethernet, DDR, or SpaceWire.
Familiarity with radiation-tolerant or space-qualified FPGA devices and SEU mitigation techniques.
Experience with verification methodologies such as UVM, constrained-random testing, or formal verification.
Integration experience with SoCs, embedded processors, or mixed-signal systems.
Exposure to synthesis, static timing analysis, and power or thermal considerations for flight hardware.
Comfort with scripting and command-line tools such as Tcl and Python.
Prior experience in aerospace, space systems, or other high-reliability domains.

Responsibilities

Provide technical direction and guidance to FPGA engineers, and mentor teammates on architecture, RTL design, verification strategies, timing closure, and debugging.
Grow the team's technical capability through knowledge sharing, design reviews, and hands-on collaboration.
Drive adoption of best practices in FPGA development, reliability, and design verification.
Lead contributions to the architecture, RTL implementation, and verification of high-reliability FPGA designs.
Own significant portions of FPGA designs from concept through implementation, timing closure, lab bring-up, integration, and verification.
Contribute directly to RTL coding, constraint development, simulation, and problem resolution.
Help establish and refine FPGA development processes for design, verification, timing analysis, and integration.
Work with embedded software, hardware engineering, systems engineering, and other stakeholders to integrate FPGA designs with avionics and vehicle systems.