FPGA Verification Engineer Level 5 - Linthicum

Northrop Grumman•Linthicum Heights, MD

2d•$185,900 - $278,900•Onsite

About The Position

Northrop Grumman Space Systems is currently seeking a FPGA Verification Engineer-Level 5 for the development of digital subsystems and products. In this position the Verification Engineer will be leading FPGA verification efforts across multiple programs. This individual will be responsible for defining, implementing and scaling a modern verification methodology using VUnit, while also providing technical leadership and team oversight. The ideal candidate brings deep expertise in FPGA verification, strong leadership skills and experience in aerospace/defense or other high-reliability environments. Their primary task is to verify that FPGA designs meet the necessary specifications and operate as intended, identifying and correcting potential issues early in the design process. This role will work out of our Linthicum, MD campus.

Requirements

Bachelor’s degree with 12 years of experience, a master’s degree with 10 years of experience or a PhD with 7 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.
Proficiency in hardware description languages (e.g., SystemVerilog, Verilog, VHDL).
Familiarity with industry-standard tools (e.g. Synopsys, Mentor Graphics).
Knowledge and hands-on experience with VUnit.
Digital subsystem, ASIC, FPGA and/or digital board development experience and knowledge essential
Candidate must have good communication skills, strong interpersonal skills, and good oral and written presentation skills
Must be able to mentor and coach early career Engineers as needed
Must be able to obtain and maintain Secret or Top-Secret level security clearance, per business requirements
Experience developing test plans, participating in reviews, test development and RTL debug
No Clearance required to start but must have the ability to obtain and maintain a TS/SCI clearance w/SAP
U.S. Citizenship required

Nice To Haves

Advanced Degree with at least 10+ years of professional experience in related industry
Active DoD Top Secret Clearance or higher with SAP Access and or SCI eligibility
Experience with Verification IP integration and/or development
Experience with a coverage-driven verification methodology from planning through closure
Experience in creating comprehensive documentation of test cases, verification plans/methods, and test results for review and future reference.
Development of scripts and use of verification tools like VUnit or proprietary frameworks to streamline and automate verification processes.
Knowledge of industry standard bus or I/O interfaces
Experience with VHDL Assertions
FPGA/ASIC design and/or development process experience
Experience with scripting languages (Python, Tcl, Makefile)
Knowledge of digital signal processing
Knowledge of working with Xilinx and MicroChip FPGAs (Kintex, Zynq ultrascale+, RTG4, etc)
Effective communication with systems and software teams for requirements, ICDs, handoffs, etc.
Able to work effectively within a development team to understand system level inter-dependence and design constraints
Active Top Secret clearance a plus

Responsibilities

Create verification plans from system requirements, define scope, methodology, coding standards, coverage goals, and traceability matrices.
Design and roll out a reusable, VUnit‑based verification environment, including libraries, VIP, and a modular test‑bench architecture that can be shared across programs.
Set up CI pipelines (e.g., Jenkins) for nightly regression, coverage collection, and metric reporting; automate test generation, execution, and result analysis with Python/Tcl scripts.
Write VHDL test benches and VUnit test suites; develop functional‑coverage models, assertions, directed and random stimulus, and verification IP as needed.
Perform root‑cause analysis of simulation failures, coordinate hardware bring‑up and lab validation, and work with designers to resolve bugs quickly.
Deliver functional‑coverage, code‑coverage, and requirements‑traceability reports; ensure all verification metrics meet program exit criteria before design hand‑off.
Lead a team of FPGA verification engineers across multiple programs, coach junior staff on verification best practices, and promote design‑for‑verification (DFV) throughout the organization.
Partner with design, systems, firmware, and software groups to guarantee complete verification coverage; actively participate in SRR, PDR, CDR, and TRR reviews.
Identify technical risks early, define mitigation plans, and enforce adherence to internal FPGA development processes, security standards, and DoD clearance requirements.
Drive adoption of industry‑standard verification methodologies, evaluate emerging tools, and contribute to process‑optimization initiatives that enhance productivity and product quality.