FPGA Engineer II

RTX•McKinney, TX

4d•$68,900 - $131,100•Onsite

About The Position

The FPGA Engineer II supports a development program within the Airborne RF Electronics Design Department. The role develops FPGA designs across major vendors and device families, including AMD, Altera, and Microchip. Designs support applications such as multi-gigabit interfaces, RF and electro-optical DSP, controls, data links, embedded processing, and processor interfaces. The engineer collaborates with circuit card designers and systems engineers on requirements, architecture, algorithm modeling, partitioning, coding, simulation, and place and route. Designs are verified against requirements using directed and constrained-random methodologies, with support expected from requirements definition through production release. Design documentation and configuration management are required. This is an onsite position in McKinney, Texas. The position requires an active and existing DoD Secret clearance after the first day, and U.S. citizenship is required because only U.S. citizens are eligible for a security clearance.

Requirements

Typically requires a STEM degree and a minimum of 2 years of prior relevant experience.
Experience in at least 4 of the following areas: FPGA/ASIC design using VHDL and/or Verilog, or FPGA/ASIC verification using SystemVerilog; experience with AMD (Xilinx), Altera, and/or Microchip (Microsemi) devices and tools such as AMD Vivado, Altera Quartus Prime Pro, or Libero; hands-on integration and debugging of FPGA/ASIC in a lab; Git source-code management, design reviews, and code release in a team development environment; Python or C programming; CI/CD pipelines; digital simulation using Questa, RivieraPro, or similar tools.
Ability to obtain and maintain a U.S. government-issued security clearance after starting employment; U.S. citizenship is required.
An active and existing DoD Secret clearance is required after day one.

Nice To Haves

One or more advanced degrees in Electrical Engineering or a related STEM major; a suitable degree may count as 2 years of work experience.
FPGA/ASIC design experience with embedded systems using ARM, MicroBlaze, or NIOS processors.
Experience with gigabit serial interfaces and multi-gigabit transceivers (MGTs).
Constrained-random verification in UVM using SystemVerilog.
Experience with High Level Synthesis (HLS).
Experience with vector processors and/or GPUs.
Experience with timing closure, clock-domain crossing and reset-domain crossing analysis, and constraint development.
Demonstrated ability to lead design efforts and/or small teams.
Familiarity with AI LLM-assisted workflows.
Knowledge of encryption/decryption standards such as AES, RSA, and ECC.

Responsibilities

Provide full lifecycle support for production-quality FPGA designs using one or more major vendors and device families, including AMD (Xilinx), Altera, and Microchip (Microsemi).
Generate FPGA designs for multi-gigabit serial interfaces, RF DSP, controls, data links, embedded processing, and processor interfaces.
Assist with architecture development of FPGA-based systems, including determining parts, interfaces, and Concept of Operations (CONOPS).
Design and code in VHDL for reliability and maintainability.
Support design verification using self-checking techniques, directed tests, and constrained-random tests, while tracking functional and code coverage.
Understand and report execution status against planned budget and schedule using an agile framework.
Create complete documentation, including requirements, verification plans, and user guides.
Function as an individual contributor.
Clearly present work product to leadership.
Engage in professional growth and development.

Benefits

Medical insurance
Dental insurance
Vision insurance
Life insurance
Short-term disability
Long-term disability
401(k) match
Flexible spending accounts
Flexible work schedules
Employee assistance program
Employee Scholar Program
Parental leave
Paid time off
Holidays
Annual short-term and/or long-term incentive compensation programs may be available, depending on position level and collective-bargaining coverage; payments are not guaranteed.