FPGA Digital Design Engineer (6+ month Contract)

Kepler Communications•Toronto, ON

17d

About The Position

Kepler Communications is hiring an FPGA Digital Design Engineer on a contract of at least six months to develop the next generation of its satellites. The engineer will work with a team building Kepler spacecraft and design and implement FPGA code, focused either on DSP algorithms for modulating and demodulating signals on the onboard software-defined radio or on embedded systems interfacing with processors and peripherals. The role participates throughout the FPGA design flow, including simulation, synthesis, place and route, timing closure, and hardware testing.

Requirements

Bachelor’s degree in Computer Engineering, Electrical Engineering, or equivalent.
At least 5 years of working experience with FPGA/RTL design.
Experience with Verilog, SystemVerilog, or VHDL, and willingness to learn or pivot to SystemVerilog.
Experience with Xilinx FPGAs, specifically Zynq and UltraScale.
Solid understanding of timing principles, including clock domain crossing and timing closure.
Strong scripting skills, such as Python, Tcl, csh, or bash.
Experience with FPGA tools such as Vivado or Quartus and HDL simulation tools such as ModelSim.

Nice To Haves

Master of Science in Computer or Electrical Engineering, or equivalent.
Experience with coherent digital demodulation of waveforms such as BPSK, QPSK, or QAM.
Experience with memory-mapped interfaces such as AXI, Wishbone, or Avalon.
Experience with high-speed transceivers for protocols such as JESD204B, PCIe, or SATA.
Experience with linting tools, Questa Sim, or Riviera-Pro.
Experience with Xilinx Versal and RFSoC.
Experience designing printed circuit boards.
Knowledge of radio-frequency electronics design.

Responsibilities

Develop custom IP for new features of Kepler satellite digital payloads.
Iterate on current DSP and interface designs to improve reliability.
Work with IP core vendors to integrate new functionality into Kepler designs.
Work with lead engineers to develop communications and network architecture for the future satellite constellation.
Participate in conceptual design studies of new spacecraft.
Participate in all phases of FPGA design flow, including simulation, synthesis, place and route, timing closure, and hardware testing.

Benefits

Competitive compensation with an equity plan.
Health, dental, and vision insurance, including dependent coverage.
Unlimited vacation.
Supportive parental leave policy.
Company-wide holiday shutdown.
Semi-annual company-wide parties and frequent in-office team events.
Relocation packages available for approved roles.
$1,500 annual professional development fund.
Fully stocked Toronto office kitchen with snacks, drinks, games, and kitchen appliances.
Town Halls, Celebration Calls, and company-wide events.