Foundary Business Manager

Normal Computing Corporation • Palo Alto, CA

21d

About The Position

Normal Computing is seeking an experienced Principal / Manager for Foundry Partnership & ASIC Program Management to lead strategic foundry engagements and end-to-end execution for upcoming advanced-node ASIC projects. This role will be the first dedicated liaison between the engineering team and foundry partners, specifically Samsung Foundry, and will own the commercial, technical, and operational lifecycle from contract execution and PDK/IP alignment through milestone tracking, quality assurance, and tapeout delivery for Q4 2027.

The position combines foundry relationship management, ASIC technical program management, quality and reliability planning, and coordination with packaging partners. It serves as the primary contact for foundry customer engineering and business development teams, while aligning internal design teams and external partners to manage schedules, technical issues, production monitoring, and tapeout readiness.

Requirements

• At least 8 years of experience in the semiconductor industry.
• At least 3–4 years directly in foundry relationship management, ASIC technical program management, or physical design implementation.
• Hands-on track record delivering tapeouts in sub-8nm advanced process nodes.
• Solid understanding of PDKs, design rules, third-party IP licensing (including PCIe, CXL, LPDDR, and SerDes), and EDA sign-off flows such as DRC, LVS, and STA.
• Strong negotiation skills.
• Fluency in English and Korean.

Nice To Haves

• Direct experience with Samsung Foundry ecosystems and tapeout flows.

Responsibilities

• Drive strategic relationships, NDAs, MSAs, and Foundry Access Agreements with a leading global foundry and ecosystem partners, including IP vendors, EDA tool providers, and OSATs.
• Serve as the primary point of contact for the foundry’s Customer Engineering and business development teams, and lead regular business and technical reviews.
• Evaluate MPW runs versus dedicated full-mask schedules to optimize cost, lead times, and risk.
• Build, manage, and drive the multi-phase tapeout schedule from RTL freeze, synthesis, and place-and-route through final DRC/LVS sign-off and GDSII submission.
• Coordinate internal RTL, architecture, design verification, and physical design teams with external foundry support teams to proactively address technical blockers.
• Establish contingency strategies for schedule deviations, design modifications, and IP integration delays to meet the 2027 tapeout deadline.
• Establish silicon validation, ESD, and latch-up testing criteria in alignment with foundry guidelines.
• Oversee process monitor data, Wafer Acceptance Testing, yield metrics, and defect-density tracking during silicon fabrication.
• Coordinate with OSAT vendors on package substrate development, assembly, and post-silicon bring-up readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed