Foundary Business Manager

Normal Computing Corporation • Palo Alto, CA

22d

About The Position

Normal Computing is seeking an experienced Principal / Manager for Foundry Partnership & ASIC Program Management to lead strategic foundry engagements and end-to-end execution for upcoming advanced-node ASIC projects. This person will be the first dedicated liaison between the engineering team and foundry partners, specifically Samsung Foundry, and will own the commercial, technical, and operational lifecycle, from contract execution and PDK/IP alignment through milestone tracking, quality assurance, and tapeout delivery targeted for Q4 2027.

The role manages foundry relationships and commercial agreements, coordinates internal design teams with external foundry support, drives ASIC tapeout schedules and risk mitigation, establishes silicon qualification and reliability plans, monitors fabrication quality and yield, and coordinates packaging and post-silicon bring-up readiness. Normal Computing is an applied AI company developing foundational hardware and software for the semiconductor industry, critical AI infrastructure, and broader systems, working across New York City, Mountain View, London, Copenhagen, and Seoul.

Requirements

• At least 8 years of semiconductor industry experience.
• At least 3–4 years of direct experience in foundry relationship management, ASIC technical program management, or physical design implementation.
• A hands-on track record of delivering tapeouts in sub-8nm advanced process nodes.
• Solid understanding of PDKs, design rules, third-party IP licensing (such as PCIe, CXL, LPDDR, and SerDes), and EDA sign-off flows, including DRC/LVS/STA.
• Strong negotiation skills.
• Fluency in English and Korean.

Nice To Haves

• Direct experience with Samsung Foundry ecosystems and tapeout flows is strongly preferred.

Responsibilities

• Drive strategic relationships, NDAs, MSAs, and Foundry Access Agreements with a leading global foundry and ecosystem partners, including IP vendors, EDA tool providers, and OSATs.
• Serve as the primary contact for the foundry’s Customer Engineering and business development teams, and lead regular business and technical reviews.
• Evaluate MPW runs versus dedicated full-mask schedules to optimize cost, lead times, and risk.
• Build, manage, and drive the multi-phase tapeout schedule from RTL freeze, synthesis, and place-and-route through final DRC/LVS sign-off and GDSII submission.
• Coordinate internal RTL, architecture, design verification, and physical design teams with external foundry support teams to address technical blockers.
• Establish contingency strategies for schedule deviations, design modifications, and IP integration delays to meet the 2027 tapeout deadline.
• Establish silicon validation, ESD, and latch-up testing criteria in alignment with foundry guidelines.
• Oversee process monitor data, Wafer Acceptance Testing, yield metrics, and defect density tracking during silicon fabrication.
• Partner with OSAT vendors on package substrate development, assembly, and post-silicon bring-up readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed