Formal Verification Engineer - New College Grad 2027

NVIDIA•Santa Clara, CA

2d•$100,000 - $189,750

About The Position

As a Formal Verification Engineer at NVIDIA, you will work on the formal verification team for industry-leading chips. You will own formal verification of RTL units for next-generation chip designs, requiring a deep understanding of unit architecture and microarchitecture. The role calls for strong analytical skills, a computer architecture background, and experience applying effective verification methodologies. You will develop formal verification test plans and environments, apply formal verification techniques to establish correctness of digital designs, debug RTL failure scenarios, and automate verification processes. You will also review formal setups and proofs with design and verification teams. This is a new college graduate position for 2027. The base salary range is $100,000–$166,750 for Level 1 and $116,000–$189,750 for Level 2, determined in part by location, experience, and pay for similar positions. The position is also eligible for equity and benefits. Applications will be accepted at least until October 31, 2026. The posting is for an existing vacancy.

Requirements

Bachelor’s or master’s degree in computer science, computer engineering, electrical engineering, mathematics, or equivalent experience.
Strong analytical skills to solve difficult problems.
Knowledge of or experience with formal verification techniques.
Strong knowledge of CPU/GPU architectures and digital logic.
Understanding of abstraction techniques for effective verification.
Hands-on experience with HDLs such as Verilog or SystemVerilog.
Ability to understand RTL quickly.
Understanding of temporal logic assertions.
Excellent communication skills and ability to collaborate effectively with team members.

Nice To Haves

Experience with formal verification tools such as Jasper, IFV, SMV, or SPIN.

Responsibilities

Develop comprehensive formal verification (FV) test plan documents.
Identify key behaviors of the design under test (DUT) and create a verification plan.
Develop verification environments, including environment assumptions, assertions, and cover properties, in the context of the verification plan.
Apply various formal verification techniques to prove the correctness of digital designs.
Debug RTL to identify failure scenarios.
Develop scripts to automate the verification process.
Review formal setups and proofs with design and verification teams.