SambaNova’s Design Verification team verifies the RDU, its chip for AI workloads. The team builds SystemVerilog and UVM environments for chip-level control and initialization, including sequencing, state transitions, clocking, and recovery, and works with architects, RTL designers, and firmware engineers. As a new graduate Design Verification Engineer, you will write testbenches, tests, checkers, and coverage in SystemVerilog and UVM for RDU features. You will run regressions, debug simulation failures, and work with RTL designers to identify and fix bugs before tape-out.
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Job Type
Full-time
Career Level
Entry Level