Emulation Verification Engineer

Apple • San Diego, CA

1d

About The Position

The Emulation Verification Engineer will help create, deploy, and support advanced emulation environments for large Wireless SoCs. The role involves bringing up designs and mixed-signal components on the Palladium emulation platform, then executing a detailed emulation test plan. The engineer will contribute to verification using monitors, checkers, and design and verification code, and will work closely with cross-functional teams across the chip design effort.

Requirements

• Bachelor’s degree.
• Experience with SystemVerilog, Verilog, or UVM.
• Experience with emulation bring-up, debugging, and verification.
• Understanding of the tool flow from RTL to emulation.
• Good understanding of a standard emulator flow (Palladium, Veloce, or Zebu) or an FPGA flow (Xilinx or Altera).
• Proven design verification or silicon validation skills.
• Experience writing synthesizable SystemVerilog or Verilog code and SystemVerilog assertions.
• Experience with SystemVerilog verification environments, including C/C++ DPI and UVM.
• Experience with a scripting language such as Perl, Python, or TCL.
• Excellent analytical and debugging skills.

Nice To Haves

• Hands-on usage of low-power methodologies, preferably UPF-based.
• Experience in UVM acceleration.

Responsibilities

• Bring up large Wireless SoCs and their mixed-signal components on an emulation platform in collaboration with the emulation team.
• Develop and use monitors and checkers on the emulation platform.
• Prepare and execute the emulation test plan and review it with cross-functional teams.
• Collaborate with Design, Architecture, Power, Silicon Validation, Performance, and Software teams.
• Develop design and verification code that supports emulation activities using Verilog, SystemVerilog, and UVM.
• Port designs onto the Palladium platform and execute the detailed emulation test plan.

What This Job Offers

• Job Type: Full-time