Emulation Front-End Infrastructure Engineer

NVIDIA•Santa Clara, CA

10d•$136,000 - $264,500•Onsite

About The Position

NVIDIA’s Emulation Infrastructure team builds scalable hardware development platforms and compilation flows that enable pre-silicon validation of complex designs. The Emulation Front-End Infrastructure Engineer will work onsite in Santa Clara, California, owning and evolving front-end compilation, synthesis, and flow infrastructure for NVIDIA hardware emulation platforms. The role develops and automates robust flows, supports EDA tools and methodologies, and improves performance, reliability, scalability, usability, and observability across a large-scale hardware development environment. The engineer will run and debug compilation and synthesis regressions, collaborate with logic designers to maintain RTL stability, and work with internal design teams and EDA vendors to resolve complex compilation, elaboration, synthesis, and implementation issues. The role also explores AI techniques to automate flow tasks, triage failures, identify recurring patterns, and accelerate root-cause analysis.

Requirements

A bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience, with at least 5 years of relevant experience; alternatively, a master’s degree in a related field with at least 3 years of relevant experience.
Experience with RTL compilation, synthesis, front-end design implementation, and flow automation.
Working proficiency in Verilog and SystemVerilog, including the ability to read, debug, and modify RTL for emulation needs.
Strong understanding of RTL elaboration, synthesis, logic optimization, and front-end design methodologies.
Hands-on experience with front-end synthesis and compilation EDA tools, including Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE.
Strong automation and scripting skills in Python, Perl, Tcl, shell scripting, and Makefile-based flows.
Experience running high volumes of jobs on distributed compute farms using workload schedulers such as LSF or Slurm, and using revision-control systems such as Perforce or Git.
Strong debugging, problem-solving, communication, and cross-functional collaboration skills.

Nice To Haves

Experience with hardware-emulation compilation flows and runtime bring-up or debugging.
Deep expertise with Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE.
Experience building scalable regression, reporting, monitoring, and flow-debug infrastructure.
Experience building AI/LLM agents or automation that can classify tool logs, diagnose failures, and drive automated recovery.
Experience partnering directly with EDA vendors to resolve complex tool, methodology, or performance issues.

Responsibilities

Own and evolve front-end compilation, synthesis, and flow infrastructure for NVIDIA hardware emulation platforms.
Develop, maintain, and automate compilation and synthesis flows using scripting and EDA tools.
Run, analyze, and debug regular compilation and synthesis regressions, and help maintain RTL design stability with logic designers.
Explore and apply AI techniques to improve flow automation, triage compilation failures, identify recurring failure patterns, and accelerate root-cause analysis.
Evaluate, deploy, and support EDA tools and methodologies for front-end implementation and emulation compilation.
Diagnose complex compilation, elaboration, synthesis, and implementation issues in collaboration with internal design teams and EDA vendors.
Improve flow performance, reliability, scalability, usability, and observability across a large-scale hardware development environment.