Embedded Systems Engineer, High Speed DSP

Google•Haifa, CA

1d•$192,000 - $278,000

About The Position

The Embedded Systems Engineer, High Speed DSP role focuses on architecting and defining low-level firmware and control loops for Google's physical-layer communications silicon. The position sits at the intersection of digital signal processing, hardware-software co-design, and real-time systems, leading development of adaptive algorithms, forward error correction (FEC), and link-telemetry frameworks. The work translates complex communications theory into reliable, real-time silicon execution and connects high-performance hardware pipelines with Google's AI infrastructure. The role contributes to Google's TPU technology and AI/ML hardware acceleration, developing custom silicon solutions for AI/ML applications. It is part of the AI and Infrastructure team, which delivers AI and infrastructure capabilities at scale for Google users, Google Cloud customers, and Googlers.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
10 years of industry experience in embedded systems/firmware, communication systems engineering, or digital signal processing (DSP) development.
Experience developing embedded software in C/C++ for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
Expertise in Forward Error Correction (FEC) algorithms and advanced modulation schemes.
Track record defining firmware framework specifications, register maps, and Silicon Life-cycle Management telemetry for high-volume networking or AI silicon.
Background in wireless communications with deep domain knowledge of channel modeling, noise mitigation, and digital transceiver architectures.

Responsibilities

Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, including the balance between hardware-fixed logic and programmable firmware.
Architect in-situ monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, including real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to integrate silicon firmware with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks, including register maps, driver latencies, and boot-up sequencing, that affect Google's AI infrastructure.