EDA Engineer

Arizona State University•Tempe, AZ

6d•Onsite

About The Position

The EDA Engineer will support the Southwest Advanced Prototyping (SWAP) Hub, one of eight regional innovation hubs in the Department of Defense’s Microelectronics Commons program led by Arizona State University. The hub brings academic, industry, and government partners together to accelerate microelectronics innovation and prototyping, bridging research and scalable manufacturing for national defense and commercial applications. The engineer will develop, maintain, and optimize electronic design automation (EDA) tool flows and design-enablement infrastructure for projects across the organization. The role includes gathering and managing EDA tool, PDK, and IP requirements; selecting and deploying EDA software; maintaining IP libraries and their integration with relevant PDKs; enabling MPW access; and supporting users from onboarding through prototype delivery. The engineer will troubleshoot technical issues and improve processes in collaboration with Design Managers, Design Engineers, IT, vendors, cross-hub teams, and external partners. The position also represents SWAP Hub within the Cross-Hub Enablement Solutions (CHES) organization, supporting governance, access controls, and compliance for EDA tools. The engineer will work with IT on cloud-based and on-premises solutions and support reporting to ASU SWAP Hub leadership, NSTXL, and the Department of Defense Microelectronics Commons. The role requires microelectronics design-enablement and semiconductor design-flow experience, knowledge spanning the silicon lifecycle, hands-on experience with major EDA tools, and working knowledge of Linux, Python, and shell scripting. This is a grant-funded, full-time position based on the Tempe campus. The salary range is $86,900–$125,000 per year, depending on experience. The position is funded by the Department of Defense and requires candidates to meet the definition of a U.S. person under 22 C.F.R. § 120.62 and 15 C.F.R. § 772.1. Additional screening may apply. The role involves a climate-controlled office, extended periods in a stationary position, and some time in cleanroom and semiconductor-processing environments. Driving is not required.

Requirements

Bachelor’s degree and three years of experience appropriate to the area of assignment or field, or an equivalent combination of experience and/or training.
Meet the definition of a U.S. person under 22 C.F.R. § 120.62 and 15 C.F.R. § 772.1.
Strong background in microelectronics design enablement, semiconductor design flows, and cloud-based compute infrastructure.
Hands-on experience with industry-leading EDA tools, including Cadence, Synopsys, Siemens EDA, Ansys, or Keysight.
Working knowledge of Linux, Python, and shell scripting.
Strong analytical, troubleshooting, and cross-functional collaboration skills.
Ability to work with diverse design teams, IT, and external partners to optimize and maintain EDA and compute environments.

Nice To Haves

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Understanding of the silicon lifecycle, including analog/mixed-signal and digital tools, physical verification, sign-off tools, and advanced packaging.
Familiarity with tools from EDA vendors such as Cadence, Siemens, Synopsys, Ansys, and Keysight.
Familiarity with Linux, Python, shells, and cloud computing.
In-depth knowledge of analog/mixed-signal and digital design tools and flows, physical verification, and sign-off methodologies.
Experience integrating and managing IP libraries, PDKs, and MPW access.
Familiarity with cloud-compute environments and modern automation workflows.
Strong interpersonal and communication skills and the ability to work effectively in academic, industry, and government collaborations.

Responsibilities

Lead and develop teams and partners focused on EDA tool and cloud-compute support for diverse design projects.
Define and maintain efficient EDA tool flows with clear execution timelines and deliverables.
Collect, validate, and manage EDA, PDK, and IP requirements across multiple project teams.
Maintain IP libraries, manage PDK downloads, and enable MPW access for design teams.
Provide user support and troubleshoot technical issues related to EDA tools, compute environments, and design workflows.
Collaborate with Design Managers, Engineers, IT, and vendors to optimize design-enablement infrastructure and resolve technical issues.
Represent SWAP Hub in CHES to support governance, access, and compliance around EDA tools.
Support reporting to ASU SWAP Hub leadership, NSTXL, and the Department of Defense Microelectronics Commons.
Develop and maintain process flows and RACIs to improve operational efficiency and cross-team collaboration.