EDA Tools Software Engineer

Intel•Hillsboro, OR

1d•Onsite

About The Position

As a member of the PTD Litho Frame Automation Team (FRAT) in Logic Technology Development (LTD), the EDA Tools Software Engineer is responsible for process design rule definition and for constructing and validating lead certification tape-in collaterals for Intel’s next-generation process technology and products. The role validates and creates VLSI layouts that enable fundamental process development. The engineer supports quality assurance of FRAT designs across Intel process nodes, troubleshoots design and PDK verification issues using complex physical design flows, and develops software code for cell designs and test cases. The role also supports the CAD design development and distribution of LTD tape-in collateral libraries for all Intel process technology nodes, including experimental pathfinding projects. It involves working with experts in lithography, integration, devices, test chips, tape-out, and OPC/RET to develop designs for process implementation, monitoring, improvement, and development. These designs are refined during development and then made available for high-volume manufacturing. The position requires an on-site presence in Hillsboro, Oregon. The listed annual U.S. salary range is $95,640–$181,940, with pay depending on location and job-related factors. Intel states that its total compensation package includes competitive pay, stock bonuses, and health, retirement, and vacation benefits.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus at least 6 months of hands-on domain experience demonstrated through internships, academic projects, coursework, or hands-on training; or a master’s degree in one of these fields or a related field, with no prior professional experience required.
Coursework or background should include VLSI design or CAD, programming in Python or C++, semiconductor device physics or basic electrical circuit theory, and silicon manufacturing flows.

Nice To Haves

Familiarity with semiconductor processing or engineering, or computer science, through coursework, internship, or work experience.
Experience with VLSI circuit mask design layout or verification through coursework, internship, or work experience.
Knowledge of basic solid-state physics, optics, and IC process flow through coursework, internship, or work experience.
Programming skills in a high-level programming language.
Familiarity with UNIX/Linux platforms.
Experience with Cadence Virtuoso, Klayout, and tools such as Calibre DRV or Calibre.
Knowledge of design rule checks (DRC), ICV, or IC Validator software tools.
Experience with custom design and verification tools, debugging, and flow development.
Strong communication and collaboration skills for cross-functional teamwork.
Proactive mindset focused on continuous improvement and learning.

Responsibilities

Verify that VLSI layouts adhere to complex layout design rules.
Own quality assurance of FRAT designs across Intel process nodes.
Troubleshoot design and process design kit (PDK) verification issues using complex physical design flows, including industry-standard and Intel tools and flows.
Write and update software code for cell designs and test cases, verification, and package design content for distribution.
Develop and support the LTD tape-in collateral library CAD design for all Intel process technology nodes, including experimental pathfinding projects.
Collaborate with cross-functional experts to extract, execute, and construct designs for process implementation, monitoring, improvement, and development.
Help refine designs during development and prepare them for high-volume manufacturing.