EDA Tools Software Engineer

Intel Corporation•Hillsboro, OR

1d•$95,640 - $181,940•Onsite

About The Position

As a member of Intel’s PTD Litho Frame Automation Team (FRAT) in Logic Technology Development (LTD), the EDA Tools Software Engineer is responsible for process design rule definition and for constructing and validating lead certification tape-in collaterals for Intel’s next-generation process technology and products. The role creates and validates VLSI layouts that enable fundamental process development. The engineer supports quality assurance of FRAT designs across Intel process nodes, troubleshoots design and Process Design Kit (PDK) verification issues in complex physical design flows, and develops software and verification content for cell designs, test cases, and package designs. The role also develops and supports LTD’s tape-in collateral library across Intel process technology nodes, including CR experimental path-finding projects. The position collaborates with experts across Litho, Integration, Device, Test Chip, Tape Out, and OPC and RET teams. Designs and constructs produced by the team support process implementation, monitoring, improvement, and development; they are refined during development and ultimately made available for high-volume manufacturing.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus at least 6 months of hands-on domain experience demonstrated through internships, academic projects, coursework, or hands-on training; OR a master’s degree in one of these fields or a related field with no prior professional experience.
Coursework and background should include VLSI design or CAD, programming in Python or C++, semiconductor device physics or basic electrical circuit theory, and silicon manufacturing flows.

Nice To Haves

Familiarity with semiconductor processing or engineering, or computer science, through coursework, an internship, or work experience.
VLSI circuit mask design layout and/or verification experience through coursework, an internship, or work experience.
Basic knowledge of solid-state physics, optics, and IC process flow.
Programming skills in a high-level programming language.
Familiarity with UNIX/Linux platforms.
Experience with Cadence Virtuoso, Klayout, and tools such as Calibre DRV or Calibre.
Knowledge of design rule checks (DRC), ICV, or IC Validator software tools.
Experience with custom design and verification tools, debugging, and flow development.
Strong communication and collaboration skills for cross-functional teamwork.
A proactive mindset focused on continuous improvement and learning.

Responsibilities

Verify VLSI layout adherence to complex layout design rules and own quality assurance of FRAT designs across all Intel process nodes.
Troubleshoot design and PDK verification issues involving complex physical design flows, including industry-standard and Intel tools and flows.
Write and update software code for cell designs and test cases, verification, and package design content for distribution.
Develop and support the LTD Tape-in Collateral Library for all Intel process technology nodes, including CR experimental Path Finding projects.
Collaborate with Litho, Integration, Device, Test Chip, Tape Out, and OPC and RET experts to direct, extract, and execute designs and constructs used for process implementation, monitoring, improvement, and development.