EDA Engineer

Arizona State University•Tempe, AZ

1d•$86,900 - $125,000•Onsite

About The Position

The Southwest Advanced Prototyping (SWAP) Hub, one of eight regional innovation hubs in the Department of Defense’s Microelectronics Commons program led by Arizona State University, is seeking an EDA Engineer. The Hub brings together academic, industry, and government partners to accelerate microelectronics innovation and prototyping, bridging research and scalable manufacturing for national defense and commercial applications. The EDA Engineer drives the development, maintenance, and optimization of EDA tool flows supporting project execution. The role collects and manages EDA tool requirements, optimizes EDA software selection and deployment, and maintains the IP library and its integration with relevant PDKs. The engineer works closely with Design Managers, Design Engineers, IT, cross-hub teams, vendors, and external partners to improve the customer experience from onboarding through prototype delivery, troubleshoot issues, and improve processes. The position represents SWAP Hub within the CHES (Cross-Hub Enablement Solutions) organization to support governance, access controls, and compliance for EDA tools. It manages cloud-based and on-premises solutions in partnership with IT and supports diverse design projects across the silicon lifecycle, including materials and modeling, analog/mixed-signal and digital design, verification, and advanced packaging. The role also supports reporting to ASU SWAP Hub leadership, NSTXL, and the Department of Defense Microelectronics Commons. This position is grant-funded by the Department of Defense and requires candidates to meet the definition of a US person under 22 C.F.R. § 120.62 and 15 C.F.R. § 772.1. Additional screening may apply. The position is based at the Tempe campus; driving is not required.

Requirements

Bachelor’s degree and three years of experience appropriate to the area of assignment or field, or an equivalent combination of experience and/or training that provides comparable knowledge, skills, and abilities.
Meet the definition of a US person under 22 C.F.R. § 120.62 and 15 C.F.R. § 772.1.
Strong background in microelectronics design enablement, semiconductor design flows, and cloud-based compute infrastructure.
Hands-on experience with industry-leading EDA tools, including Cadence, Synopsys, Siemens EDA, Ansys, or Keysight.
Working knowledge of Linux, Python, and shell scripting.
Strong analytical, troubleshooting, and cross-functional collaboration skills.

Nice To Haves

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Understanding of the silicon lifecycle through analog/mixed-signal and digital tool physical verification, sign-off tools, and advanced packaging.
Familiarity with tools from leading EDA vendors such as Cadence, Siemens EDA, Synopsys, Ansys, and Keysight.
Familiarity with Linux, Python, shells, and cloud compute.
In-depth knowledge of analog/mixed-signal and digital design tools and flows, physical verification, and sign-off methodologies.
Experience integrating and managing IP libraries, PDKs, and MPW access.
Familiarity with cloud-compute environments and modern automation workflows.
Strong interpersonal and communication skills, with the ability to work effectively in multi-institutional academic, industry, and government collaborations.

Responsibilities

Lead and develop teams and partners focused on EDA tool and cloud-compute support for diverse design projects.
Define and maintain efficient EDA tool flows with clear execution timelines and deliverables.
Collect, validate, and manage EDA, PDK, and IP requirements across multiple project teams.
Maintain IP libraries, manage PDK downloads, and enable MPW access for design teams.
Provide user support and troubleshoot technical issues related to EDA tools, compute environments, and design workflows.
Collaborate with Design Managers, Engineers, IT, and vendors to optimize design-enablement infrastructure and resolve technical issues.
Represent SWAP Hub in CHES to ensure governance, access, and compliance around EDA tools.
Support reporting to ASU SWAP Hub leadership, NSTXL, and the Department of Defense Microelectronics Commons.
Develop and maintain process flows and RACIs to improve operational efficiency and cross-team collaboration.