Director, Verification

kepler•San Jose, CA

2d•$270,000 - $310,000

About The Position

Kepler is seeking a Director, Verification to lead pre-silicon verification and post-silicon validation for its products. This leadership role combines VLSI verification expertise with responsibility for building and inspiring high-performing teams. The Director will drive verification programs from early definition through product development, tapeout, post-silicon bring-up, validation, and production release. The role owns verification strategy and methodology, including test plans, testbench development, automated flows, regressions, coverage closure, and tapeout signoff. It partners with architecture, RTL design, DFD, and software teams, and leads verification and emulation engineers. The position also defines post-silicon validation and production qualification, and tracks verification health through metrics and milestone reviews.

Requirements

B.Tech, M.Tech, or MS in EE, Electronics, VLSI Design, or a related field.
15+ years of hands-on VLSI front-end verification experience with multiple successful SoC/ASIC tapeouts.
Deep expertise in UVM-based verification, including testbench architecture, scoreboarding, coverage modeling, and constrained-random verification.
Strong SystemVerilog skills, including interfaces, clocking blocks, SVA, covergroups, and testbenches.
Thorough understanding of SoC-level verification challenges, including CDC, power-aware verification (UPF), memory subsystems, and interrupt and reset validation.
Solid knowledge of industry-standard on-chip and memory protocols and VIP integration.
Hands-on experience with industry-standard formal verification and simulation tools.
Hands-on experience with functional, code, and assertion coverage closure.
Good scripting skills in Python, Perl, Shell, and Makefile.
Exposure to hardware/software co-verification (TLM/SystemC).
Experience with post-silicon validation, debug, and production test correlation.
Excellent leadership and communication skills, with a proven ability to lead teams in a fast-paced environment.
Proven record from pre-silicon verification through production release.

Nice To Haves

Experience with emulation platforms.
Familiarity with ML-assisted verification, such as coverage prediction and test prioritization.
Understanding of DFT-aware verification, including scan, BIST, JTAG, and debug architecture.
Knowledge of verification challenges in 3D innovations.
Familiarity with AI workloads and their memory demands.
Prior startup experience with lean teams and aggressive timelines.

Responsibilities

Own the end-to-end pre-silicon verification strategy, including test plans, testbench development, automated flows and regressions, coverage closure, and tapeout signoff.
Define and run verification plans covering functional coverage, assertion-based verification, constrained-random stimulus, formal verification, and AI-assisted flows.
Co-lead model-based testing, emulation, and FPGA prototyping for pre-silicon verification, software development, and architectural validation.
Coordinate with architecture, RTL design, DFD, and software teams to align verification plans with design intent.
Define and run post-silicon bring-up, validation, debug, and production qualification.
Develop verification IP (VIP) and protocol checkers.
Set UVM-based testbench architecture standards and a coverage-driven verification methodology.
Build and maintain regression infrastructure, including nightly and weekly pipelines, coverage merge, and automated triage.
Track and publish verification health metrics, including coverage, assertion density, and regression health, and run regular milestone reviews.
Build, lead, and mentor a team of verification and emulation engineers.