Digital Physical Design Engineer

Keysight Technologies, Inc.•Colorado Springs, CO

5d•Onsite

About The Position

Keysight has an opportunity for a Physical Design R&D engineer responsible for the physical implementation and tape release of digital and mixed-signal ASICs. The engineer will perform module-level and SoC-level implementation from RTL to GDS and help deliver ASICs that meet customer functionality, schedule, and quality requirements. The role is part of Keysight Laboratories, based in Colorado Springs, Colorado, and involves collaborating with cross-functional teams on ASIC development. The position spans the ASIC design lifecycle, including definition, architecture, digital logic design, IP validation, synthesis, physical implementation, and sign-off. The engineer will solve complex design and development problems, apply product and customer-application knowledge to develop and validate design methods, work with industry foundries, and develop tool flows while driving vendors toward milestones.

Requirements

Bachelor’s or master’s degree in electrical or computer engineering.
Typically 0–2 years of relevant experience.
Strong electrical engineering fundamentals and experience in ASIC design, digital architectures or systems, digital circuit synthesis, and verification of large and mixed-signal ASIC designs.
Desire to identify and debug problems.
Leadership skills to build credibility and respect and influence teams and partners toward improved execution, return, and productivity.
Strong teamwork and written and verbal communication skills.

Nice To Haves

Experience with Innovus and Tempus.
Experience with task automation and scripting.
Experience with digital and analog ASIC design flows, methodologies, and processes.
Experience with DFT architecture and implementation.
Fluency with object-oriented programming.
Ability to multitask and engage with multiple projects, engineers, and partnerships.

Responsibilities

Perform module-level and SoC-level implementation of digital and mixed-signal ASICs from RTL to GDS.
Participate in the full range of ASIC design activities, including definition, architecture, digital logic design, IP validation, and synthesis.
Perform floor planning, place and route, timing closure, static timing analysis (STA), formal verification, low-power design, clock distribution, EMIR analysis, and physical verification.
Complete sign-off checks, interface with industry foundries, and deliver GDS.
Collaborate with cross-functional teams and guide architecture decisions using physical-design constraints.
Develop tool flows and drive vendors to achieve milestones.
Solve design and development problems, including customer application issues, and develop and validate design concepts and methods.