DFT Engineer (CE-64000845)

Cirrus Logic • Chandler, AZ

11d

About The Position

As a DFT Engineer in Cirrus Logic’s mixed-signal audio development team, you will perform initial test planning, insert memory BIST and scan, improve test coverage, and deliver test patterns to the product test group. You will work on mixed-signal SoCs for consumer mobile audio markets, supporting several expanding product lines.

The role involves defining, implementing, and reviewing DFT features in a collaborative team environment. It also includes verifying MBIST and ATPG patterns through gate-level simulations, analyzing test costs, and supporting silicon bring-up on ATE.

Requirements

• MSEE with 2+ years of experience, or BS with relevant industry experience.
• Strong hands-on working knowledge of ASIC DFT design and verification.
• Experience with industry-standard DFT EDA tools such as FastScan, TestKompress, TetraMAX, or Test Compiler.
• Candidates must be able to access technical data without requiring an export license; Cirrus Logic is unable to sponsor or obtain export licenses for this role.

Nice To Haves

• Experience with Verilog, SystemVerilog, or VHDL.
• Understanding of low-power test techniques and architectures.
• Knowledge of scripting languages such as Perl, Python, or TCL.
• Experience with synthesis, static timing analysis, and developing timing constraints.
• Strong oral and written communication skills.
• Experience with flows and automation.
• Ability to work independently and as part of a team.
• A curious and inquiring mind, with commitment to follow through on finding answers.
• Experience debugging and root-causing silicon problems.

Responsibilities

• Define, implement, and review DFT features within a collaborative team.
• Generate, insert, and verify Memory BIST logic.
• Perform scan insertion and ATPG pattern generation.
• Help develop and review DFT timing and equivalence-checking constraints.
• Verify MBIST and ATPG patterns with gate-level simulations.
• Identify and improve test coverage gaps.
• Perform test cost planning and analysis.
• Deliver MBIST and ATPG patterns to the product test group.
• Support silicon bring-up on ATE.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level