DFT and Test Engineer

Celestica • Richardson, TX

1d • Onsite

About The Position

The DFT and Test Engineer runs the testability review inside the design phase. This role is responsible for checking test point access, boundary scan chains, debug access, and provisioning access against established DFT rules, while modeling coverage against the MTRS before layout freeze. Operating at the intersection of Hardware, Software, Firmware, and Test Operations, this position acts as the crucial gatekeeper for testability as an inherent design property and supports functional test definition and early build debug for the assigned site. This position focuses strictly on testability as a core design property and is not a Test Development or Fixture Design role.

Requirements

• Strong technical expertise in Design for Testability (DFT) concepts, checking test point access, boundary scan chains, debug access, and provisioning access.
• Proven hands-on proficiency with Boundary Scan, In-Circuit Testing (ICT), and coverage analysis tooling.
• Solid capability in modeling structural and functional test coverage against coverage standards (e.g., MTRS).
• Excellent collaborative problem-solving skills to disposition hardware and software findings across multi-disciplinary teams.
• Strong cross-functional communication skills to work effectively with schematic, layout, software, firmware, and test engineering stakeholders.
• 4 to 8 years of experience in Design for Testability (DFT) or Test Engineering in a complex electronics environment.
• Bachelor’s degree in Electrical Engineering, Electronic Engineering, or a related technical discipline.

Responsibilities

• Review schematic and layout against the DFT rule set before freeze, raising findings alongside supporting evidence behind the rule.
• Model structural and functional coverage to report gaps against the MTRS, and verify achieved coverage on the first fixture while recording differences against initial claims.
• Collaborate cross-functionally with schematic/layout engineers, software/firmware teams, the program TRL, site test engineering, and the DFT manager to resolve coverage gaps via test point additions, chain corrections, or agreed alternatives.
• Support functional test definition and early build debug in tandem with the Test Readiness Lead (TRL) and on-site test SMEs.
• Propose DFT rule changes derived from test escapes and fixture rework feedback to drive ongoing design standards.
• Own key deliverables—including testability reviews, coverage models against MTRS, DFT findings with formal dispositions, achieved coverage evidence documentation, and rule change proposals.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level