Design Verification Intern

quadric•Burlingame, CA

9d•$50 - $57•Onsite

About The Position

This internship offers hands-on experience in verifying a next-generation processor architecture. The intern will work directly with the hardware team on building supercomputer technology for the Edge. The role involves supporting the Design Verification team in documenting test plans, writing and debugging tests, and generating coverage for Quadric's GPNPU. This provides exposure to real verification methodologies used on CPU and GPU-class designs and close collaboration with architects and designers.

Requirements

Currently pursuing a Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or a related field.
Familiarity with verification methodologies for CPU or GPU designs.
Proficient in either SystemVerilog, SystemC, or C/C++ (UVM is a plus).
Prepared to collaborate with architects and designers to document test plans, write and debug tests, and generate coverage.
Demonstrated capability in problem-solving, debugging, and clear technical communication.

Nice To Haves

Coursework or project experience with computer architecture, RTL design, ML systems, or performance engineering.
Exposure to assembly or low-level code generation.
Adept with scripting languages like Python and using LLMs to get things done.

Responsibilities

Support Verification Planning: Collaborate with architects and designers to document test plans for the GPNPU.
Write & Debug Tests: Write and debug tests against the processor's architecture and micro-architecture.
Generate and analyze coverage to help assess verification completeness.
Collaborate Across the Team: Work closely with hardware architects and designers to understand design intent and clarify verification requirements.
Communicate findings, blockers, and technical questions clearly to the team.