Design Verification Engineer

Apple•Cupertino, CA

1d•Hybrid

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for verifying complex digital IPs. Work with the system architects and digital designers, making block level specifications clear and precise. Use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions. Own the creation of the verification test benches using formal verification and UVM based simulation. Build the test cases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks. Participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve bug free designs on the first tape out. Collaborate in developing precise design specifications for digital control blocks. Use design specifications to create block and chip level verification plans. Architect and create block level verification elements. Assist in architecting chips and system level verification environments. Use System Verilog and UVM to develop drivers, tests, reference models and checkers. Debug test failures and work with designers to develop fixes. Using functional and code coverage to track progress and gauge tape out readiness.

Requirements

Utilizing System Verilog to create block level verification elements.
Utilizing Verilog, VHDL to debug design issues and to root cause bugs.
Utilizing Digital Hardware Simulation to develop checkers and tests.
Utilizing Object Oriented Programming, C to understand and debug C program executions on the chips.
Utilizing Python, Perl, or algorithms to develop automation flows.
Utilizing Chip simulations on CAD software including debugging of simulation failures.
Utilizing Finite State Machine design and verification experience to ensure design quality.

Responsibilities

Responsible for verifying complex digital IPs.
Work with the system architects and digital designers, making block level specifications clear and precise.
Use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions.
Own the creation of the verification test benches using formal verification and UVM based simulation.
Build the test cases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks.
Participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve bug free designs on the first tape out.
Collaborate in developing precise design specifications for digital control blocks.
Use design specifications to create block and chip level verification plans.
Architect and create block level verification elements.
Assist in architecting chips and system level verification environments.
Use System Verilog and UVM to develop drivers, tests, reference models and checkers.
Debug test failures and work with designers to develop fixes.
Using functional and code coverage to track progress and gauge tape out readiness.