Design Verification Engineer

Apple•Cupertino, CA

4h•$149,987 - $194,700•Onsite

About The Position

Responsible for verifying complex digital IPs. Work with the system architects and digital designers, making block level specifications clear and precise. Use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions. Own the creation of the verification test benches using formal verification and UVM based simulation. Build the test cases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks. Participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve bug free designs on the first tape out. Collaborate in developing precise design specifications for digital control blocks. Use design specifications to create block and chip level verification plans. Architect and create block level verification elements. Assist in architecting chips and system level verification environments. Use System Verilog and UVM to develop drivers, tests, reference models and checkers. Debug test failures and work with designers to develop fixes. Using functional and code coverage to track progress and gauge tape out readiness.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field
Utilizing System Verilog to create block level verification elements
Utilizing Verilog, VHDL to debug design issues and to root cause bugs
Utilizing Digital Hardware Simulation to develop checkers and tests
Utilizing Object Oriented Programming, C to understand and debug C program executions on the chips
Utilizing Python, Perl, or algorithms to develop automation flows
Utilizing Chip simulations on CAD software including debugging of simulation failures
Utilizing Finite State Machine design and verification experience to ensure design quality

Responsibilities

Verifying complex digital IPs
Making block level specifications clear and precise
Building verification plans to exercise functional, performance, stress cases, and error conditions
Creating verification test benches using formal verification and UVM based simulation
Building test cases using System Verilog Assertions and constrained random UVM testcases
Participating in code reviews of other blocks in the chips
Developing precise design specifications for digital control blocks
Creating block and chip level verification plans
Architecting and creating block level verification elements
Assisting in architecting chips and system level verification environments
Developing drivers, tests, reference models and checkers using System Verilog and UVM
Debugging test failures and working with designers to develop fixes
Using functional and code coverage to track progress and gauge tape out readiness