Design Verification Engineer

Apple•Cupertino, CA

1d•Hybrid

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Understand the design specification and extract attributes of the design from the specification. Create UVM based tests and sequences based on attributes to stress the design and verify correctness of the RTL. Have discussions with Design Engineers regarding missing specifications, corner cases/interesting scenarios where the design might show unexpected behavior. Debug root cause of failure and reporting the bug to design engineer using waveform analysis/log files. Work with EDA vendors to use VIP/tool in our test benches. Develop Coverage points to analyze coverage and writing Assertions for the design. Understand the design, extracting attributes from the design specification and verifying correctness of the RTL design.

Requirements

Experience in Hardware Verification Language (HVL) and Hardware Design Language (HVL) including System Verilog or Verilog for Verification Environment and test development.
Utilizing knowledge of HVL methodology (UVM, OVM, and VMM) for constrained random test development.
Applying verification skills in problem solving, constrained random testing, and debugging.
Understanding of reusable verification framework to help speedup verification process.
Utilizing knowledge of digital logic design, chip architecture and microarchitecture to help analyze and debug RTL design.
Applying AMBA protocol knowledge in developing monitor/checker and analyzing RTL design
System Verilog Assertion (SVA) for verification.
Programing in C/C++ for embedded CPU verification and system modeling
Writing scripts in languages including Perl or Python.
Defining coverage space and writing coverage model to measure verification quality and find verification holes.

Responsibilities

Understand the design specification and extract attributes of the design from the specification.
Create UVM based tests and sequences based on attributes to stress the design and verify correctness of the RTL.
Have discussions with Design Engineers regarding missing specifications, corner cases/interesting scenarios where the design might show unexpected behavior.
Debug root cause of failure and reporting the bug to design engineer using waveform analysis/log files.
Work with EDA vendors to use VIP/tool in our test benches.
Develop Coverage points to analyze coverage and writing Assertions for the design.
Understand the design, extracting attributes from the design specification and verifying correctness of the RTL design.