Design Verification

Apple•Cupertino, CA

23h•$150,400 - $225,300•Onsite

About The Position

Work with RTL designers and architects to understand and review specifications and architecture and extract features as part of the verification team supporting Apple's Display Technologies portfolio for the next-generation of Apple products. Develop verification strategies, including test plans and coverage requirements to cover the functional and performance requirements of the design. Design, implement, and maintain scalable and re-usable SystemVerilog UVM based test-benches for SOC and sub-system level verification. Update environment scripts (Python) to support new test configurations. Write and maintain test cases using directed/constrained random test generation and assertion-and formal-based verification. Create coverage models and tracking coverage metrics to ensure 100% coverage goals are met. Run RTL and gate-level simulations investigating failures from daily/nightly simulations run at chip/block level, using log analysis and waveform tools (lndago/SimVision) to review them with the RTL designers and file bug reports as appropriate. Build and maintain automated regressions; Coordinate with architects/designers for end-to-end validation; Create and maintain up-to-date documentation for test plans, attributes, and verification environment. Support scripted automation flows as needed to enhance the verification methodology.

Requirements

Using Verilog and SystemVerilog for testbench and constrained random test development to build the verification infrastructure.
Testplan and coverage plan development in order to plan the test scenarios and the features that need to be covered.
Using C or C++ to be used for reference model or checker development to check the correctness of the design behavior.
Perl, Python, or tcl scripting to set up the regression automation flow which facilitates running test suites.
Knowledge of Digital Electronics and RTL design concepts to understand the design microarchitecture.
Experience with simulators and waveform viewers for running tests, debugging digital designs and finding bugs.
Understanding and knowledge of writing System Verilog Assertions (SVA) for simulations-based and formal verification to be used for checker development.

Responsibilities

Develop verification strategies, including test plans and coverage requirements.
Design, implement, and maintain scalable and re-usable SystemVerilog UVM based test-benches for SOC and sub-system level verification.
Update environment scripts (Python) to support new test configurations.
Write and maintain test cases using directed/constrained random test generation and assertion-and formal-based verification.
Create coverage models and tracking coverage metrics.
Run RTL and gate-level simulations investigating failures.
Build and maintain automated regressions.
Coordinate with architects/designers for end-to-end validation.
Create and maintain up-to-date documentation for test plans, attributes, and verification environment.
Support scripted automation flows as needed to enhance the verification methodology.