Design Verification

Apple•Cupertino, CA

20h•$150,400 - $225,300•Onsite

About The Position

Responsible for low power verification of various Apple SOC. Review power related aspects of design and architecture specifications of SOCs and corresponding Power Manager SOCs and work closely with design, architecture, software teams to identify attributes that need to be tested. Develop test plan and coverage plans and develop, define test benches needed for executing on the test plan. Develop specific test plans to verify low power functionality of various system on chip designs. Develop specific test plans to verify hardware within system on chip responsible for restoring hardware to correct state as chip goes through power state transitions. Create directed and random tests for testing the integration of power manager. Write tests in C programming language for testing the hardware. Create system Verilog behavioral models and stimulus to test the simulation of system on chip with power manager chip together. Write scripts in Perl and Python programming languages to automate the verification of test plan. Create scripts and regressions to track and maintain chip simulations. Run chip level simulations using CAD software. Use AXI,AMBA Protocols to verify integration of various blocks within chip and debug failing test cases. File bug reports for simulation failures and track them until fix and closure. Work independently and manage deliverables to align with project goals and support cross functional engineering efforts.

Requirements

Bachelor’s Degree or foreign equivalent in Computer Science, Computer Engineering or related field
2 years of experience in the job offered or related occupation
2 years of experience with Using digital and logic design concepts to understand the process of hardware design and verification
2 years of experience with Utilizing ARM/X86 based Computer architecture to drive processor-based verification stimulus
2 years of experience with Using data structures and algorithms to write efficient C based stimulus for chip level verification
2 years of experience with Utilizing System Verilog to create stimulus and behavioral models to validate chip design systems
2 years of experience with Using C to write chip level test cases that drive stimulus
2 years of experience with Utilizing Perl or Python to automate tasks like running testcases, failure triaging and regression maintenance
2 years of experience with Utilizing low power design fundamentals specific to CMOS based designs
2 years of experience with Using languages including UPF to describe power intent for hardware designs

Responsibilities

Review power related aspects of design and architecture specifications of SOCs and corresponding Power Manager SOCs
Work closely with design, architecture, software teams to identify attributes that need to be tested
Develop test plan and coverage plans
Develop, define test benches needed for executing on the test plan
Develop specific test plans to verify low power functionality of various system on chip designs
Develop specific test plans to verify hardware within system on chip responsible for restoring hardware to correct state as chip goes through power state transitions
Create directed and random tests for testing the integration of power manager
Write tests in C programming language for testing the hardware
Create system Verilog behavioral models and stimulus to test the simulation of system on chip with power manager chip together
Write scripts in Perl and Python programming languages to automate the verification of test plan
Create scripts and regressions to track and maintain chip simulations
Run chip level simulations using CAD software
Use AXI,AMBA Protocols to verify integration of various blocks within chip and debug failing test cases
File bug reports for simulation failures and track them until fix and closure
Work independently and manage deliverables to align with project goals
Support cross functional engineering efforts