Design Verification

AppleCupertino, CA
$174,149 - $225,300Onsite

About The Position

Design and architect specifications and work closely with design & micro-architecture teams. Understand the functional & performance goals of the design. Develop test plans, tests & coverage plans as well as define our next generation verification methodology & test benches. Communicate and collaborate with design, architecture and software teams to understand the use cases and corner conditions and drive test cases. Ensure the quality of the SoC, IP, and/or subsystem by working on one or more types of IP such as Neural Engine hardware, DRAM subsystems, memory controller logic, Encode and Decode systems for ProRes and other codec formats (such as VP9 and AV1), hardware security including cryptographic algorithm implementations), high-speed IO standards (such as PCI Express, DisplayPort, MIPI), power management and fabric infrastructure, memory cache management, and display subsystems for variety of panels and products.

Requirements

  • Master’s degree or foreign equivalent in Electrical Engineering or Computer Engineering or related field
  • 3 years of experience in the job offered or related occupation
  • 3 years of experience utilizing SystemVerilog and UVM methodology to implement scalable and reusable verification environment and test cases to verify designs
  • 3 years of experience utilizing VCS, xcelium or modelSim tools to run RTL, gate, and power aware simulations
  • 3 years of experience utilizing formal verification tools (JasperGold) for connectivity, assertion based functional and unreachability formal analysis
  • 3 years of experience utilizing coverage tools (Mentor InFact, Cadence vManager/IMC) for code and functional coverage analysis and closure
  • 3 years of experience applying C and/or C++ functional and performance models in verification
  • 3 years of experience applying knowledge in computer architecture and digital design in failure analysis and hardware debug
  • 3 years of experience utilizing waveform debug tools (Indago and Verdi) to triage and debug functional and performance issues
  • 3 years of experience developing and conducting test plans and test attributes based on design specifications
  • 3 years of experience in scripting languages PERL, tcl, and python for aiding verification
  • 3 years of experience using version control tools Perforce, Git, and Clearcase for source code control

Responsibilities

  • Design and architect specifications
  • Work closely with design & micro-architecture teams
  • Understand the functional & performance goals of the design
  • Develop test plans, tests & coverage plans
  • Define next generation verification methodology & test benches
  • Communicate and collaborate with design, architecture and software teams to understand use cases and corner conditions and drive test cases
  • Ensure the quality of the SoC, IP, and/or subsystem

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • A range of discounted products and free services
  • Reimbursement for certain educational expenses — including tuition
  • Discretionary employee stock programs
  • Discretionary restricted stock unit awards
  • Discounted Apple stock purchase through Employee Stock Purchase Plan
  • Relocation assistance
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service