Design Verification Engineer (AI Accelerated)

Persimmons•San Jose, CA

About The Position

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet. As a Senior ASIC Design Verification Engineer, you will be responsible for verifying critical blocks in the Persimmons inference chiplet that will run the smallest to largest AI models. Your primary duties and responsibilities include: You will use AI to attack the highest-cost parts of design verification. Test bench generation, stimulus creation, regression triage, coverage closure. Wherever the work is repeatable, you will replace manual effort with intelligent agents and structured automation.

Requirements

You have built real AI-driven workflows, not just chatted with a model. You've planned projects, written skills or instructions, and produced shipped automation. Even better if you've applied it to regression triage, log analysis, or test bench generation.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
7-10+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs.
Demonstrated proficiency in fabric-level and chip-level verification methodologies and best practices.
Advanced skills in SystemVerilog/Verilog, UVM methodology, and C/C++ programming, including embedded code development and validation for RISC-based processors.
Established track record in creating scalable verification flows, implementing coverage-driven verification strategies, and developing assertion-based verification frameworks.

Responsibilities

Lead comprehensive verification planning and execution for fabric-level and full-chip designs, ensuring robust validation across all design hierarchies.
Collaborate cross-functionally with architecture, firmware, and design teams to develop detailed test plans that validate implementation against specifications and requirements.
Design and implement advanced testbenches featuring constrained random stimulus generation, intelligent checkers, comprehensive scoreboards, and targeted assertions to ensure design correctness and coverage.
Architect and execute verification strategies encompassing test planning, coverage analysis, automated regression management, and data-driven insights to maximize verification efficiency and quality.
Drive verification excellence through established methodologies including structured code reviews, agile sprint planning, and systematic feature deployment processes.
Innovate verification approaches by researching and implementing next-generation methodologies, automated flows, and emerging technologies including AI-driven verification tools.