Design Verification Engineer (eInfochips Inc)

Arrow Electronics•San Jose, CA

5d•Onsite

About The Position

The Design Verification Engineer architects verification environments for ASIC SoCs and provides verification support from verification-plan definition through multi-million-gate product tapeout, including test design and development. The role develops complex self-checking testbenches with constrained-random stimulus, architects SoC test firmware, documents test plans covering ASIC features, and develops and debugs SoC ASIC platform test firmware and tests in C/C++. The engineer contributes to methodology development, plans and reviews functional and technical specifications, and implements and maintains integrated end-to-end formal verification flows. The position also involves developing or modifying automation scripts and building verification environments with assumptions, assertions, and cover properties aligned to the verification plan. It requires in-depth knowledge and experience, independent work with minimal guidance, solving complex problems, improving products or processes, and often leading project-team work or training junior staff. This is a fully onsite role in San Jose, California. The employee must be able to travel to an Arrow client office location as requested by Arrow Client leadership.

Requirements

Strong SystemVerilog and UVM expertise.
Expertise in AXI, NoC, Ethernet, PCIe, or UCIe switches.
Knowledge of ARM or RISC-V CPUs and C.
Typically, a minimum of 8 years of related experience with a four-year degree; or 6 years with an advanced degree; or equivalent experience.
In-depth knowledge and experience, ability to work independently with minimal guidance, and ability to solve complex problems.

Responsibilities

Architect verification environments for ASIC SoCs and provide verification support from verification-plan definition through product tapeout.
Design and develop tests and complex self-checking testbenches with constrained-random stimulus generation.
Architect SoC test firmware and create test-plan documentation covering ASIC features.
Develop and debug SoC ASIC platform test firmware and specific tests in C/C++.
Participate in methodology development and plan, analyze, and review functional and technical specification documents.
Implement and maintain integrated end-to-end formal verification flows.
Develop and modify scripts to automate the verification process.
Develop verification environments with assumptions, assertions, and cover properties aligned with the verification plan.
Often lead project-team work and may formally train junior staff.