Design Verification Engineer (eInfochips Inc)

Arrow•San Jose, CA

4d•Onsite

About The Position

The Design Verification Engineer architects verification environments for ASIC SoCs and provides verification support from defining the verification plan through multi-million-gate product tapeout, including test design and development. The role develops complex self-checking test benches with constrained-random stimulus, architects SoC test firmware, and creates test-plan documentation to cover ASIC features. It also involves developing and debugging SoC ASIC platform test firmware and tests in C/C++, contributing to methodology development, and planning, analyzing, and reviewing functional and technical specifications. The engineer implements and maintains an integrated end-to-end formal verification flow, develops or modifies scripts to automate verification, and develops verification environments with assumptions, assertions, and cover properties aligned with the verification plan. The position requires in-depth knowledge and independent handling of complex problems, using established solutions or new approaches as needed. The engineer applies best practices to improve products, services, or processes; may lead project teams and train junior staff; and serves as a resource to less experienced colleagues. This is a fully onsite role in San Jose, California. The employee must be able to travel to an Arrow client office location as requested by client leadership.

Requirements

Strong SystemVerilog (SV) and UVM expertise.
Expertise with AXI, NoC, Ethernet, PCIe, or UCIe switches.
Knowledge of ARM or RISC-V CPUs and C.
Typically requires at least 8 years of related experience with a four-year degree, or 6 years with an advanced degree, or equivalent experience.
Ability to work independently with minimal guidance and resolve complex problems.

Responsibilities

Architect verification environments for ASIC SoCs and provide verification support from verification-plan definition through product tapeout.
Design and develop tests and complex self-checking test benches with constrained-random stimulus generation.
Architect SoC test firmware and create test-plan documentation covering ASIC features.
Develop and debug SoC ASIC platform test firmware and specific tests in C/C++.
Contribute to methodology development and plan, analyze, and review functional and technical specification documents.
Implement and maintain an integrated end-to-end formal verification flow.
Develop or modify scripts to automate the verification process.
Develop verification environments, including assumptions, assertions, and cover properties aligned with the verification plan.
Apply best practices to improve products, services, or processes and resolve complex problems.
Lead project-team work as needed and train junior staff.
Serve as a resource for colleagues with less experience.