ASIC Developer

Ericsson • Austin, TX

24d

About The Position

Ericsson Silicon is hiring a Design Verification Engineer to architect, verify, and scale custom IPs, ASICs, SoCs, and FPGA-based platforms for communications infrastructure and Layer 1 accelerators. The role covers designs such as OSI Layer 1 accelerators, custom baseband DSPs, AI/ML inference blocks, RISC-V and ARM cores, and high-speed multi-gigabit interfaces.

The engineer will develop reusable UVM verification environments and use AI-driven methods and agentic workflows to improve test generation, debug, and coverage closure. The role works closely with architects, RTL designers, emulation teams, and system engineers to identify issues early, shorten tapeout cycles, and deliver high-quality silicon. Verification spans software simulation, hardware emulation, FPGA prototyping, and post-silicon environments, with an emphasis on evolving verification methodology through AI and automation.

Requirements

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• At least 6 years of professional design verification experience for complex ASIC, SoC, FPGA, or semiconductor products.
• Strong SystemVerilog/Verilog programming experience and hands-on expertise developing and maintaining UVM-based environments.
• Deep understanding of constrained-random verification, assertion-based verification, scoreboards, checkers, and coverage-driven signoff.
• Strong scripting and automation skills using Python, Tcl, Perl, or shell scripting; experience with Git, Jenkins, and CI/CD pipelines.
• Understanding of SoC/ASIC architectures, with exposure to Layer 1 accelerators, DSPs, AI/ML accelerators, RISC-V, or ARM Cortex processors.
• Experience verifying standard interfaces such as AMBA AXI/AHB/APB, PCIe, DDR, Ethernet, or SerDes.
• Strong written and verbal communication skills and a record of cross-functional collaboration.

Nice To Haves

• Practical experience integrating LLMs, custom coding assistants, or autonomous AI agents into hardware design, test generation, or debug workflows.
• Experience building Python automation frameworks that interface with EDA APIs or use machine learning to parse large regression datasets.
• Experience with formal or semi-formal verification tools such as JasperGold.
• Knowledge of clock-domain crossing (CDC), reset-domain crossing (RDC), low-power verification (UPF/CPF), or simulation-to-silicon correlation.
• Exposure to C/C++, RISC-V or ARM assembly, or hardware-software co-verification.
• Familiarity with Jira, Confluence, and Agile development methodologies in semiconductor environments.

Responsibilities

• Define verification plans, environments, and schedules for Layer 1 accelerator ASICs, SoCs, and FPGA platforms.
• Build reusable UVM-based verification environments using SystemVerilog, with LLM-assisted test generation and intelligent stimulus models.
• Use and help develop AI agentic frameworks to triage regression failures, draft test sequences, and parse log files.
• Drive functional, code, and assertion coverage closure using machine-learning-guided constrained-random and formal verification techniques.
• Build and maintain verification infrastructure and CI/CD automation using Python, Tcl, shell scripting, Jenkins, Git, and AI-augmented tools.
• Validate RTL and gate-level designs across software simulation, hardware emulation, FPGA prototyping, and post-silicon environments.
• Debug issues across RTL, gate-level netlists, and hardware-software co-simulation platforms using AI-assisted log analysis and pattern-recognition tools.
• Verify functionality and performance for Ericsson-proprietary interfaces and standard interfaces including AMBA, PCIe, DDR, Ethernet, and high-speed SerDes.
• Contribute to verification methodology improvements, incorporating generative AI and automation tools into daily workflows.
• Mentor junior engineers in verification techniques and AI/agentic development tools.
• Collaborate with architects, RTL designers, emulation teams, and system engineers.

Benefits

• Annual bonus opportunity through a Short-Term Variable Compensation Plan.
• Three medical plan options and a dental plan option, with company credits toward premiums for employees and eligible covered dependents.
• 401(k) plan with an automatic 3% company contribution and matching contributions up to 4% when the employee contributes at least 5% of eligible pay.
• Company credits for basic life insurance, accidental death and dismemberment coverage, and short- and long-term disability coverage.
• Option to participate in the Ericsson Stock Purchase Plan.
• At least 15 days of accrued vacation, up to 3 personal days annually, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually.
• Up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.
• Financial wellness programs, educational assistance, matching gifts, and recognition programs.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior