Design Verification Engineer - Early Career
About The Position
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Connectivity group is the industry leader in PHY devices for AI, cloud datacenter and enterprise infrastructure. Our devices today power the full range of network connectivity from the optics of the AI GPU boards to top of the rack optical fibers and active copper cables of the data centers and their fabrics. The Connectivity Verification Group works closely with Analog and Digital Design teams and Systems/DSP teams to incorporate and build models and testbench infrastructure for mixed signal designs and verify the digital and analog designs and micro-architectures against the system definition and requirements and also works closely with the Software team to set up the API building infrastructure and guidelines.
Requirements
- Bachelor's Degree in Electrical Engineering or a related field
- College level coursework on Digital Logic Design using Verilog, Computer Architecture, Signals, Systems and basic Digital Signal Processing
- Basic knowledge of Electrical Circuit Analysis (a course in Analog Circuits is preferred)
- A course project involving Object Oriented Programming language such as C/C++ or Java
- A course project involving principles of Verilog/VHDL/System-Verilog
Responsibilities
- Learn how the connectivity devices are dramatically impacting the AI-ML hardware revolution and the datacenters
- Learn the state-of-the-art optical PHY module architecture and design for 1.6T and 3.2T
- Learn state of the art UVM and SystemVerilog-based verification environment
- Apply the knowledge of Object-Oriented programming and its application to UVM/SystemVerilog to build new features into the verification environment as well as the test suite
- Work closely with Design teams to bring up new design features and verify them
- Learn modern day techniques of formal verification as well as code and functional coverage
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
