Design Implementation Engineer
About The Position
The Design Implementation Engineer performs design implementation activities related to place and route and/or timing closure, including floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification (LVS/DRC). The role drives tools and methodologies to achieve desired PPA metrics and performs equivalence checks, static timing analysis (STA), power optimization, and timing and functional ECO implementation. The engineer applies Broadcom’s design methodology and milestone flow to meet its criteria for right-first-time silicon. Candidates with primary expertise in place and route and/or timing (constraints and STA) may be considered. The role requires hands-on ASIC/SoC design implementation and tapeout experience, with work at both block and SoC level.
Requirements
- Extremely proficient in design implementation activities at both block and SoC level.
- Well experienced in floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification and/or constraints development, constraints validation, timing analysis, and closure.
- Experience with formal verification, timing analysis, and ECO implementation.
- Hands-on experience with timing analysis and place-and-route tools for ASIC/SoC design.
- Good problem-solving skills.
- Ability to work independently as a self-starter.
- Experience working in a global team and dynamic environment.
- Ability to learn and adapt to new tools and methodologies quickly.
- Excellent communication skills.
- At least 1–2 ASIC tapeouts in 7nm or lower technologies.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field and 8+ years of related experience; or a master’s degree in one of these fields or a related field and 6+ years of related experience.
Nice To Haves
- Experience with tools such as PrimeTime, ICC2, Innovus, Caliber, and LEC.
- Full-chip tapeout experience based on 7nm and lower technologies.
Responsibilities
- Perform place-and-route and/or timing-closure design implementation activities.
- Carry out floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis, timing closure, and physical verification (LVS/DRC).
- Drive tools and methodologies to achieve desired PPA metrics.
- Perform equivalence checks, STA, and power optimization.
- Implement timing and functional ECOs.
- Apply Broadcom’s design methodology and milestone flow to support right-first-time silicon.
- Develop and validate constraints, where applicable.
Benefits
- Discretionary annual bonus eligibility.
- Competitive new-hire equity grant opportunity and annual equity awards, subject to applicable plan documents and award agreements.
- Medical, dental, and vision plans.
- 401(k) participation with company matching.
- Employee Stock Purchase Program (ESPP).
- Employee Assistance Program (EAP).
- Company-paid holidays.
- Paid sick leave and vacation time.
- Paid Family Leave and other leaves of absence in accordance with applicable laws.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
