Design Implementation Engineer

Broadcom • San Jose, CA

1d

About The Position

The Design Implementation Engineer performs design implementation activities related to place and route and/or timing closure, including floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification (LVS/DRC). The engineer drives tools and methodologies to achieve desired PPA metrics and performs equivalence checks, static timing analysis (STA), power optimization, and timing and functional ECO implementation.

The role applies Broadcom's design methodology and milestone flow to meet its criteria for achieving right-first-time silicon. Candidates with primary expertise in place and route and/or timing, including constraints and STA, may be considered. The position requires hands-on ASIC/SoC design implementation and timing-analysis experience, with experience taping out ASICs in 7nm or lower technologies.

Requirements

• Extremely proficient in design implementation activities at both block and SoC level.
• Well experienced in floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification and/or constraints development, constraints validation, timing analysis, and closure.
• Experience with formal verification, timing analysis, and ECO implementation.
• Hands-on experience with timing-analysis and place-and-route tools for ASIC/SoC design.
• Should have worked on tapeout of at least 1–2 ASICs in 7nm or lower technologies.
• Good problem-solving skills; self-starter able to work independently.
• Experience working in a global team and dynamic environment.
• Ability to learn and adapt to new tools and methodologies on the fly.
• Excellent communication skills.
• BS in Electrical Engineering, Computer Engineering, or a related field and 8+ years of related experience, or an MS in one of those fields and 6+ years of related experience.

Nice To Haves

• Experience with tools such as PrimeTime, ICC2, Innovus, Caliber, and LEC is highly desirable.
• Full-chip tapeout experience based on 7nm and lower technologies is highly preferred.

Responsibilities

• Perform design implementation activities for place and route and/or timing closure.
• Carry out floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification (LVS/DRC).
• Drive tools and methodologies to achieve desired PPA metrics.
• Perform equivalence checks, static timing analysis (STA), and power optimization.
• Implement timing and functional ECOs.
• Apply Broadcom's design methodology and milestone flow to meet criteria for right-first-time silicon.

Benefits

• Discretionary annual bonus
• Competitive new-hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence in accordance with applicable laws

What This Job Offers

• Job Type: Full-time
• Career Level: Senior