SSG Design Engineering Intern (Fall 2026)

Cadence Systems•San Jose, CA

8h•Onsite

About The Position

The Cadence Silicon Solutions Group (SSG) is experiencing significant growth with its industry-leading Digital IP, including processor cores, DSPs, Memory Controllers, Network on Chip (NoC), and IO solutions. These configurable and extensible IP solutions are designed for SOCs and Chiplets targeting diverse applications such as hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. Cadence SSG is seeking graduates to join its R&D teams in San Jose, CA, for an internship opportunity as a Design Engineering Intern. This role offers the chance to work at a leading company in computational software, semiconductor design IP, and system verification hardware, contributing to impactful projects within the SSG Team. The internship will focus on Digital Design or Design Verification tasks related to the Janus NoC IP product.

Requirements

Currently enrolled in MS/BS program with a major in Electrical Engineering, Computer Engineering, or a similar major.
Deep understanding of Digital Design and/or Design Verification Fundamentals.
Excellent automation skills using Tcl, Perl, shell scripting.
Excellent oral and written communications skills.

Nice To Haves

Exposure to design automation tools is a plus.

Responsibilities

Work on aspects of the logic design of the Janus NoC, including RTL implementation in System Verilog.
Simulate and debug RTL logic.
Run synthesis, place & route, and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.
Assist with developing test plans for design verification.
Write functional tests (UVM) and verification monitors (SVA).
Debug failures, analyze coverage information, and script Design Verification flows.
Work closely with the Design, Verification, and Physical Design teams.