SSG Design Engineering Intern (Fall 2026)

Cadence Design Systems•San Jose, CA

2d•$35 - $62•Onsite

About The Position

The Cadence Silicon Solutions Group (SSG) is experiencing significant growth with its industry-leading Digital IP, including processor cores, DSPs, Memory Controllers, Network on Chip (NoC), and IO solutions. These configurable and extensible IP solutions are designed to meet the needs of SOCs and Chiplets for various applications. Our clients are among the world's most innovative companies, developing advanced electronic products for sectors such as hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. The Cadence SSG Team is seeking graduates to join our R&D teams in San Jose, CA. This internship offers a unique opportunity to work as a Design Engineering Intern at a leading company in computational software, semiconductor design IP, and system verification hardware. Join the SSG Team and contribute to visible, impactful projects. This Design Engineering Intern role will focus on Digital Design or Design Verification tasks related to the Janus NoC IP product. Digital Design projects involve working on the logic design of the Janus NoC, which may include RTL implementation in System Verilog based on a given micro-architecture, simulating and debugging RTL logic, and utilizing Electronic Design Automation (EDA) tools for synthesis, place & route, and analysis of timing, area, and power. Design Verification Team projects involve contributing to the verification of the Janus NoC. This includes assisting in developing test plans, writing functional tests (UVM) and verification monitors (SVA), debugging failures, analyzing coverage data, and scripting Design Verification workflows. The Design Engineering Intern will collaborate closely with the Design, Verification, and Physical Design teams.

Requirements

Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar major.
Deep understanding of Digital Design and/or Design Verification Fundamentals.
Excellent automation skills using Tcl, Perl, shell scripting.
Excellent oral and written communications skills.

Nice To Haves

Exposure to design automation tools is a plus.
Ideal candidates should be from local schools near the office.

Responsibilities

Work on aspects of the logic design of the Janus NoC, including RTL implementation in System Verilog.
Simulate and debug RTL logic.
Run synthesis, place & route, and other EDA tools to study and achieve timing, area, and power goals.
Assist with developing test plans for design verification.
Write functional tests (UVM) and verification monitors (SVA).
Debug failures and analyze coverage information.
Script Design Verification flows.
Work closely with the Design, Verification, and Physical Design teams.