SSG Design Engineering Intern (Fall 2026)

Cadence Design Systems•San Jose, CA

2d•$35 - $62•Onsite

About The Position

The Cadence Silicon Solutions Group (SSG) is experiencing significant growth in the adoption of its industry-leading Digital IP, including processor cores, DSPs, Memory Controllers, Network on Chip (NoC), and IO solutions. These configurable and extensible IP solutions are designed to meet the requirements of SoCs and Chiplets for a diverse range of applications. Our clients are among the world's most innovative companies, delivering advanced electronic products, from chips to boards to complete systems, for dynamic market applications such as hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. The Cadence SSG Team is seeking graduates to join our R&D teams in San Jose, CA. This is an exceptional opportunity to serve as a Design Engineering Intern at a global leader in computational software, semiconductor design IP, and system verification hardware. Join the SSG Team and contribute to impactful work. This Design Engineering Intern position will focus on Digital Design tasks or Design Verification tasks related to the Janus NoC IP product. (a) Digital Design projects will involve working on aspects of the logic design for the Janus NoC. This may include RTL implementation of a specified micro-architecture using System Verilog, simulating and debugging RTL logic, and utilizing synthesis, place & route, and other Electronic Design Automation (EDA) tools to analyze and achieve timing, area, and power objectives. (b) Design Verification Team projects will focus on the verification of the Janus NoC. Responsibilities include assisting in the development of test plans, writing functional tests (UVM) and verification monitors (SVA), debugging failures, analyzing coverage data, and scripting Design Verification flows. The Design Engineering Intern will collaborate closely with the Design, Verification, and Physical Design teams.

Requirements

Currently enrolled in an MS/BS program with a major in Electrical Engineering, Computer Engineering, or a similar field.
Deep understanding of Digital Design and/or Design Verification Fundamentals.
Excellent automation skills using Tcl, Perl, shell scripting.
Excellent oral and written communications skills.

Nice To Haves

Exposure to design automation tools is a plus.
Ideal candidates should be from a local school near the office.

Responsibilities

Work on aspects of the logic design of the Janus NoC, including RTL implementation in System Verilog.
Simulate and debug RTL logic.
Run synthesis, place & route, and other EDA tools to achieve timing, area, and power goals.
Assist with developing test plans for the Janus NoC.
Write functional tests (UVM) and verification monitors (SVA).
Debug failures and analyze coverage information.
Script Design Verification flows.
Work closely with the Design, Verification, and Physical Design teams.