Design Engineer I - II or Senior Design Engineer, Texas Institute for Electronics

University of Texas at Austin • Austin, TX

1d • Onsite

About The Position

The Texas Institute for Electronics (TIE) is a public-private partnership focused on advancing semiconductor systems and defense electronics. TIE is developing cutting-edge semiconductor manufacturing equipment and processes to define future roadmaps in areas like advanced packaging, logic, memory, heterogeneous integration, and chip cooling. They are seeking motivated individuals to join their team and contribute to these goals. TIE is part of The University of Texas at Austin's Cockrell School of Engineering, a leading institution in technology innovation and engineering education with extensive research centers and a strong industry recruitment rate. The university offers a dynamic work environment and a gateway to Austin's vibrant culture, with a commitment to making a lasting impact.

Requirements

• Bachelor’s degree in Electrical Engineering, Semiconductor Physics, Materials Science, or related field.
• Strong understanding of semiconductor device physics and mixed signal circuit design.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork skills, with the ability to collaborate effectively with cross-functional teams.
• Ability to thrive in a fast-paced environment and manage multiple projects simultaneously.
• Proficiency in EDA software for circuit and/or package design.
• Applicants must be authorized to work in the United States on a full-time basis for any employer without sponsorship.

Nice To Haves

• Master’s degree or Doctoral degree in semiconductor engineering fields such as Electrical Engineering, Semiconductor Physics, or other relevant disciplines.
• Prior experience in semiconductor design, product engineering, Test, or process integration.
• Experience with semiconductor Packaging : Power/thermal IC , Stress/strain interconnect optimization, or fan-in/out substrate design.
• Solid understanding of semiconductor packaging technologies, including wire bonding, flip-chip, wafer-level packaging, and 3D integration a plus.
• Strong background or interest in DFT/DFM (Design For Test/Manufacturing) methodologies and Built-In Self-Test (BIST) techniques.
• Experience in a startup or research and development (R&D) environment.
• Relevant education and/or industry experience may be substituted as appropriate (for Eng II, or Senior).

Responsibilities

• Design and develop mixed signal circuits, test vehicles, and test structures to support the development of TIE's 3D-ADK (Assembly Design Kit).
• Help develop workflows, 2.5D/3D modeling methods, and standard cells to comprehend and optimize Power/Thermal/Mechanical/Signal Integrity/RF impacts of multi-chiplet, heterogeneous micro-systems.
• Work with Product and Test engineering teams to comprehend and design in requirements to ensure performance, yield, reliability, and support BIST (Built in Self-Test) methodologies.
• Collaborate closely with EDA vendors and their tool/modeling solutions to evaluate effectiveness & drive improvements in their tool offerings and capability.
• Develop and implement advanced models to analyze and predict the effects of semiconductor packaging on device performance, reliability, and lifetimes.
• Improve automation of circuits and layouts to support standard cells and structures using Python, C+/+, MATLAB or other scripting languages.
• Participate in industry ‘design standards’ workshops & consortiums to promote an open access 3DHI manufacturing chiplet eco-system.
• Bring key aspects back into TIE designs and workflows to ensure we are compatible with industry trends.
• Collaborate with internal and external design teams to ensure package compatibility with semiconductor die and system-level requirements.
• Design and execute experiments to evaluate and optimize packaging performance, reliability, and manufacturability.
• Conduct rigorous simulation and 3DHI modeling studies to verify the performance, reliability, and testability of semiconductor packaging designs. (multi-physics modeling includes: Power, Thermal, Mechanical, Signal Integrity, RF, Analog/Digital performance)
• Stay current with industry trends and emerging technologies in semiconductor packaging and design integration to drive innovation and continuous improvement.

Benefits

• Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
• Voluntary Vision, Dental, Life, and Disability insurance options
• Generous paid vacation, sick time, and holidays
• Teachers Retirement System of Texas, a defined benefit retirement plan, with 7.75% employer matching funds
• Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
• Flexible spending account options for medical and childcare expenses
• Robust free training access through LinkedIn Learning plus professional conference opportunities
• Tuition assistance
• Expansive employee discount program including athletic tickets
• Free access to UT Austin's libraries and museums with staff ID card
• Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card
• Relocation assistance may be available.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level