CPU RTL Design Lead

Google•Austin, TX

4h•$240,000 - $333,000

About The Position

Be part of a team developing custom silicon solutions that power Google's direct-to-consumer products. The role contributes to the innovation behind Google's products by shaping next-generation hardware experiences, with a focus on performance, efficiency, and integration. Google's team brings together AI, software, and hardware to research, design, and develop technologies that make computing faster, seamless, and more powerful. The position participates in CPU subsystem development, with emphasis on front-end design, microarchitecture, and RTL for the next-generation CPU. Individual pay is determined by job-related skills, experience, and relevant education or training. The listed US compensation is $240,000–$333,000, plus a 25% bonus target, equity, and benefits.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
15 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with SystemVerilog RTL and related design processes such as Lint and UPF.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience leading front-end design for modern processor components or AI accelerators.
Experience with ARM Instruction Set Architecture.
Experience with SoC design, architecture, and integration.

Responsibilities

Participate in developing the CPU subsystem, including front-end design focused on microarchitecture and RTL for the next-generation CPU.
Propose performance-enhancing microarchitecture features and work with Software, Architect, and Performance teams on trade-off studies.
Communicate the pros and cons of microarchitecture enhancements and deliver production-quality designs that meet PPA goals.
Work with the Verification team to ensure design quality, and with the physical design and power teams to meet frequency, power, and area goals.
Become familiar with modern techniques, translate them into design constructs and languages, and guide and participate in performance evaluation.