ASIC/SOC Silicon Physical Design Engineer

MatX•Mountain View, CA

13h•Hybrid

About The Position

MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes.

Requirements

Bachelor of Science in Electrical Engineering or equivalent
Minimum 8 years of industry experience in ASIC Physical Design
Great interpersonal and communication skills
Strong proficiency in programming languages such as Perl, Python, and TCL
Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL to production silicon
Experience collaborating with Design, Verification, and DFT teams to structure, partition, and optimize designs for PPA through sign-off

Nice To Haves

8 years of industry experience in ASIC Physical Design
Experience working with third-party Design Services partners

Responsibilities

Contribute to MatX’s Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII
Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification)
Plan and drive intermediate and sign-off reviews.
Report execution progress towards various silicon milestones including design freeze and tapeout
Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results