ASIC Package Design Engineer

Broadcom • San Jose, CA

4d • Onsite

About The Position

Broadcom is seeking an experienced IC package-design engineer to develop complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. The role is part of a worldwide R&D team developing high-performance ASIC packages for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. Designs include SerDes at 448G and higher, 5G RF/Microwave ADC/DAC, HBM, and DDR5. The engineer will collaborate with the team to create package structures that enable new designs and contribute to design-team efficiency improvements.

Physical design (layout) is a foundational responsibility. The role also includes overall responsibility for package-design aspects such as signal integrity, power integrity, manufacturability, reliability, and thermal performance, in partnership with package engineering experts. This position requires working on-site at a Broadcom office five days a week and is not remote.

The annual base salary range is USD 143,800 to USD 230,000. The position is eligible for a discretionary annual bonus, a competitive new-hire equity grant, and annual equity awards, subject to applicable plan documents and award agreements.

Requirements

• BSEE or a similar field and 12 or more years of experience in flip-chip-BGA package design, including high-speed SerDes; alternatively, an MSEE or similar field and 10 or more years of work experience.
• Knowledge of package-level signal integrity and power integrity and the ability to apply that knowledge to package designs.
• Ability to cooperate with a worldwide team across multiple time zones, including co-design with internal team members and external vendor designers.
• Self-management and organization skills.
• Ability to work on-site at the Broadcom office five days a week.

Nice To Haves

• Cadence APD (Allegro Package Designer) experience; an equivalent tool is acceptable.
• One or more years of experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest.

Responsibilities

• Take overall design responsibility for ASIC package designs, including signal integrity, power integrity, manufacturability, reliability, and thermal considerations, in partnership with package engineering experts.
• Design critical package structures for SerDes, ADC/DAC, DDR, HBM, and related technologies.
• Schedule, prioritize, and track work across two or more projects simultaneously.
• Perform general flip-chip BGA package design and engineering.
• Manage projects and interface with customers for assigned design projects.
• Contribute to design-team efficiency improvements through process development and improvement, automation, and documentation.
• Perform physical design (layout).

Benefits

• Discretionary annual bonus
• Competitive new-hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence in accordance with applicable laws

What This Job Offers

• Job Type: Full-time
• Career Level: Senior