ASIC Package Engineer

Meta•Austin, TX

2d•$178,000 - $250,000

About The Position

Meta is seeking an experienced ASIC Package Engineer for its ASIC Packaging team. The role owns technology development and qualification readiness for the package-to-board attach process used with Meta’s custom AI/ML and networking silicon. The engineer will develop and optimize package interaction with board-attach processes, serving as the primary packaging expert for package-to-board technology development and working closely with Product Quality Engineering (PQE), Supplier Quality Engineering (SQE), and module design teams to establish a qualified, statistically controlled, high-yield manufacturing process. Meta Infrastructure designs, builds, brings up, tests, and integrates custom and general-purpose silicon-based hardware systems deployed in data centers worldwide. The team is developing packaging expertise and scalable solutions for next-generation AI/ML products and system-level performance. As die sizes grow beyond 3.3 times reticle size and packages evolve to lidless, lidded, and asymmetric stackups, board technology development is important to achieve desired yield amid package warpage, thermo-mechanical stress, and solder-joint reliability challenges. The role develops package-board processes, reliability strategies, test vehicles, specifications, design rules, and manufacturing guidelines. It also supports supplier and equipment qualification, process controls, yield improvement, and design-for-manufacturability across package, board, and system development.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
Master's degree in Materials Science, Mechanical Engineering, Electrical Engineering, or a related field, or equivalent practical experience.
8+ years of experience in semiconductor packaging with direct ownership of package-to-board assembly and reliability, package-board interaction process engineering, or electronics manufacturing.
Experience with package-board technology processes, including solder paste printing, pick-and-place, reflow soldering, and inspection methods.
Experience working with package assembly and ODM suppliers and driving process qualification and yield-improvement programs.
Experience with failure-analysis techniques for solder-joint reliability and package-board interaction-related defects.
Experience collaborating with quality engineering teams (PQE/SQE) to establish process controls and qualification requirements.
Experience with statistical process control, process capability analysis, and Design of Experiments.
Willingness to travel internationally, typically once per quarter.

Nice To Haves

Experience with reflow temperature profiling, solder alloy and paste material selection, and low-temperature solder processes.
Experience with AI/HPC or networking hardware at data-center scale.
Experience with high-temperature warpage characterization and thermo-mechanical or finite element modeling (FEM) of packages and solder joints.
Hands-on experience with SPI, AOI, and X-ray inspection systems and associated data analysis.
Experience with large-body FCBGA, flip-chip, and 2.5D/3D advanced packages and their interaction with board-assembly constraints.
Master's degree or PhD in Materials Science, Mechanical Engineering, or a related discipline.
Knowledge of packaging and assembly industry standards.
Experience with ODM, CM/EMS, OSAT, and substrate supplier engagement and audit.

Responsibilities

Own package-to-board interaction technology development for large-body advanced packages, addressing how the package, substrate, and PCB behave together through assembly and in the field.
Characterize and mitigate package warpage and coplanarity across the reflow window for large-body and lidless packages.
Drive board-level reliability (BLR) strategy for ASIC packages with quality teams, including thermal cycling, drop/shock, bend, and vibration.
Define and execute mechanical and electrical test vehicle (MTV/ETV) strategies to de-risk package-board interaction before A0 silicon availability, including solder-joint evaluation using X-ray, cross-section, and dye-and-pry at the ODM.
Represent package-board interaction and board-assembly constraints in silicon/package/PCB/system co-design and product design reviews.
Collaborate with package and module design teams to incorporate design-for-manufacturability considerations into package and board development.
Develop and implement package-board interaction process specifications, design rules, and manufacturing guidelines for new package technologies.
Evaluate and qualify package-board interaction equipment, materials, and processes to support technology roadmap requirements.
Partner with PQE, SQE, and ARD teams to establish quality standards, qualification criteria, and reliability requirements for package-board interaction processes.
Establish statistical process control (SPC) methodologies and yield-improvement initiatives for package-board interaction assembly operations.
Own package-board interaction content in FMEAs, control plans, and key-characteristic definitions; support ODM line qualification and control-run gates with PQE.
Create, conduct, and analyze Designs of Experiments (DOE) for package-board interaction development and sustaining activities.
Drive supplier engagement and qualification for package-board interaction-related materials and equipment.