ASIC Engineer, Implementation

Meta•Sunnyvale, CA

4d•$178,000 - $250,000

About The Position

Meta's Silicon Engineering organization builds custom silicon solutions for infrastructure supporting AI, data centers, and next-generation computing platforms. The Staff ASIC Implementation Engineer drives physical implementation and synthesis of complex custom ASICs from RTL through tape-out, contributing to architectural and methodological decisions that shape Meta's silicon roadmap. The role owns end-to-end implementation flows, establishes practices across teams, and partners with design, verification, and physical design teams to deliver high-performance, power-efficient silicon at scale. The engineer leads implementation methodology and flow development, supports timing closure across hierarchical partitions, and develops scripts, constraints, and automation infrastructure. The role also generates SoC floorplans at multiple levels, performs top-level connectivity and beachfront analysis, provides early implementation feedback to architecture and RTL teams, defines quality sign-off criteria, manages cross-functional risks, mentors engineers, and evaluates tools and technologies for future silicon capabilities.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
At least 8 years of experience in ASIC implementation, including logic synthesis, static timing analysis, and timing closure for complex SoC or custom ASIC designs.
Experience with industry-standard synthesis and implementation EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
Experience defining and managing synthesis constraints, including SDC and UPF, and hierarchical design methodologies.
Experience driving timing closure across multi-million-gate designs with multiple clock domains and complex timing exceptions.
Experience developing and maintaining implementation automation using scripting languages such as Tcl or Python.

Nice To Haves

Experience evaluating and integrating new EDA tools or methodologies into production implementation flows.
Familiarity with physical-aware synthesis and early floorplan co-design techniques to improve PPA outcomes.
Track record of defining implementation sign-off criteria and leading tape-out execution for complex ASIC designs.
Experience with custom ASIC implementation targeting data center, AI accelerator, or high-performance computing applications.

Responsibilities

Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, formal verification, and design-for-test integration for complex custom silicon designs.
Define and own synthesis and implementation methodology, establishing reusable flows and constraints that scale across multiple chip projects.
Drive timing closure strategies across hierarchical design partitions, resolving critical path bottlenecks with RTL designers and physical design engineers.
Develop and maintain synthesis scripts, constraint files, and automation infrastructure to improve implementation quality and reduce iteration cycles.
Generate SoC floorplans at chip, subsystem, and block levels, and enable block implementation owners to execute synthesis and physical design.
Perform top-level logical and physical connectivity and beachfront analysis, including pipe/shim and feedthrough block insertion for timing and area optimization.
Partner with architecture and RTL teams to provide early feedback on design decisions affecting area, power, and timing.
Define and enforce design rules and quality sign-off criteria across implementation milestones, ensuring readiness for tape-out.
Identify and drive resolution of cross-functional implementation risks, communicating status and trade-offs to engineering leadership and program stakeholders.
Mentor engineers on implementation methodology, synthesis best practices, and timing analysis techniques.
Contribute to long-term silicon implementation strategy by evaluating new EDA tools, flows, and technologies.