ASIC Engineer, Implementation - CAD

Meta•Austin, TX

12d•$114,000 - $172,000

About The Position

Meta is seeking an ASIC Implementation Engineer to join our Infrastructure Silicon team, focused on building custom silicon for data center applications. In this role, you will develop and maintain CAD methodologies, flows, and automation scripts that support front-end and back-end ASIC implementation, from RTL through physical design signoff. You will work closely with design, physical design, and verification engineers to enable efficient, high-quality tape-outs of Meta's next-generation infrastructure chips.

Requirements

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
2+ years of experience in synthesis & physical design
Proficiency in Python for algorithm development, engineering analysis, and automation
Experience developing CAD/EDA tools, flows, or engineering automation
Experience with RTL synthesis, physical design and PPA optimization, and knowledge of front-end and back-end ASIC tools
Experience working across cross-functional teams and vendors to debug timing, area, and power issues

Nice To Haves

Experience with DEF, netlists, floorplanning data, pin definition generation and PG-aware pin placement across hierarchical partitions
Demonstrated software engineering fundamentals: data structures and algorithms, computational geometry, and performance optimization on large datasets
Experience with multi-chiplet connectivity, feedthrough evaluation, clock/voltage/reset domains and 2.5D/3D SoIC assembly
Experience writing parsers and data models for industry-standard design formats (Verilog netlist, LEF/DEF, Liberty, SDC)
Experience building web-based engineering applications — interactive visualization frameworks, client-server architecture, session and state management

Responsibilities

Design, develop and maintain production-level CAD platforms and web-based design tooling for interactive silicon architecture exploration, floorplan visualization and automated engineering analysis
Build runtime-optimized data models, algorithms and Python APIs for large-scale design data — netlist, LEF/DEF, pin/track and connectivity databases — delivering order-of-magnitude runtime improvements over native EDA solutions
Develop tooling for generating SOC floorplans at chip, subsystem, and block level, and drive early floorplan exploration, block shaping, and area/dimension estimation to bridge architecture and implementation
Develop debug features for logical and physical connectivity and beachfront analysis on DEF and netlist data — evaluating pin locations, port configurations and connectivity consistency — including pipe/shim and feedthrough insertion for timing and area optimization
Develop automation and methodology across all FE tools (Synthesis, Physical Design, STA, Power, Floorplanning, Connectivity Analysis, Pin Planning), and partner with Design, DV, Architecture and Physical Design engineers on handoffs and timing/congestion/connectivity feedback