ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)

Boeing • Albuquerque, NM

3d • $136,850 - $266,800 • Onsite

About The Position

The Boeing Company is hiring Lead, Senior, and Principal ASIC/FPGA Design or Verification Engineers for its Boeing Electronic Products team in Albuquerque, New Mexico. The team develops digital ICs and SoCs for products across Boeing, including satellite programs, commercial airplanes, and other business units. Engineers work with cross-functional teams and partners on ASIC/FPGA design and verification for products developed at Boeing sites worldwide.

Within the LEOS team, the role supports high-performance laser gimbal control systems and involves FPGA design and embedded software development. The engineer works with hardware and software teams to define and refine system requirements and specifications and ensure software-hardware compatibility. Depending on level and assignment, the position leads designs and teams, evaluates technologies, implements and verifies digital designs, and supports prototyping, integration, and system validation.

The role is a first-shift position in Albuquerque. It requires eligibility to obtain a U.S. Secret clearance after starting, and U.S. citizenship is required for the clearance. The position also requires satisfying Boeing’s Conflict of Interest assessment and U.S. export-control compliance requirements. Boeing does not sponsor employment visas. Relocation may be offered based on eligibility.

Requirements

• Bachelor of Science degree in a directly related field, including engineering, computer science, data science, mathematics, physics, or chemistry, or equivalent non-U.S. qualifications.
• At least 9 years of ASIC/FPGA design or verification experience, or a master’s degree and at least 7 years of such experience.
• Experience defining ASIC/FPGA architectures and implementing detailed designs and functional verification using SystemVerilog, including delivery or release of production designs.
• Professional experience with hardware-based integration and testing of ASIC/FPGA designs.
• Ability to obtain a U.S. Security Clearance; U.S. citizenship is required for the clearance, and an interim and/or final U.S. Secret Clearance is required post-start.
• Ability to meet U.S. export-control compliance requirements as a U.S. Person.
• Successful completion of Boeing’s Conflict of Interest assessment process.
• For Lead level: typically 9 or more years of related work experience, or an equivalent combination of technical education and experience.
• For Senior level: typically 14 or more years of related work experience, or an equivalent combination of technical education and experience.
• For Principal level: typically 20 or more years of related work experience, or an equivalent combination of technical education and experience.

Nice To Haves

• For Senior level, 14 or more years of related work experience or an equivalent combination of education and experience.
• For Principal level, 20 or more years of related work experience or an equivalent combination of education and experience.
• Master’s degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience.
• Proven record of leading ASIC/FPGA design or verification teams, including tracking and reporting progress to stakeholders.
• Experience with hardware emulators, especially Palladium.
• Proficiency in SystemVerilog and SystemVerilog Assertions.
• Ability to create executable test plans.
• Proficiency in object-oriented programming concepts, including inheritance and polymorphism.
• Ability to create self-checking and reusable test benches from scratch.
• Experience developing functional coverage models and closing code coverage.
• Experience with high-speed SerDes interfaces such as JESD204C, PCIe, and Ethernet.
• Proficiency in scripting languages such as Make, Perl, and Python.
• Experience with revision control systems such as SVN, CVS, and Git.
• Proficiency in Linux environments.
• Familiarity with space-based design techniques and radiation mitigation.
• Demonstrated history of first-pass success with ASIC designs.
• ABET accreditation is preferred, but not required, for U.S. degrees.

Responsibilities

• Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams of design and verification engineers, and manage execution to meet program milestones.
• Collaborate with customers, system engineers, and hardware engineers to capture requirements and architect digital logic functions for mission and customer needs.
• Evaluate ASIC/FPGA technology trade-offs and select parts by weighing schedule, cost, risk, area, and power against performance.
• Implement FPGA/ASIC designs using current practices and tools, from block-level micro-architecture and HDL coding through physical design realization, including gate-level netlists for ASIC designs.
• Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed.
• Perform static timing analysis, LEC, CDC, linting, and other checks to support timely design completion.
• Develop functional coverage models and perform code coverage to verify designs in simulation.
• Create self-checking, reusable test benches and use object-oriented programming concepts and UVM components such as drivers, monitors, predictors, and scoreboards.
• Conduct FPGA-based prototyping and validation as required by program and system needs.
• Validate designs through hardware integration testing with special test equipment, test beds, and higher-level systems as needed.
• Train and mentor less senior engineers and help build effective project teams.
• Conduct unit-level testing, verification, and validation of embedded software and firmware, using debugging tools such as oscilloscopes and logic analyzers to identify and resolve issues.
• Create and maintain requirements documents, design specifications, test plans, and interface control documents.
• Support software and hardware integration from initial hardware bring-up through final system validation.
• Analyze and improve system-resource efficiency, stability, scalability, and performance, including under low-power or memory constraints.

Benefits

• Eligible employees may enroll in health insurance programs.
• Flexible spending accounts and health savings accounts are generally included among benefit program options.
• Retirement savings plans are generally included among benefit program options.
• Life and disability insurance programs are generally included among benefit program options.
• Programs providing paid and unpaid time away from work.
• Competitive base pay and variable compensation opportunities.
• Relocation may be offered based on candidate eligibility.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior