ASIC/FPGA Design and Verification Engineer – Space Electronics – (Senior or Principal) - MTV

Boeing • Mountain View, CA

11d • $164,900 - $266,800 • Onsite

About The Position

The Boeing Electronic Products team is hiring Senior- and Principal-level ASIC/FPGA Design and Verification Engineers to develop state-of-the-art digital ICs and SoCs for critical programs across Boeing. The team develops ASICs and FPGAs for applications including space and launch, avionics, missiles and weapons, strike, surveillance and mobility, and autonomous systems. Work includes custom processors, complex digitally beamformed phased arrays, and computing and networking equipment. The role supports designs developed in El Segundo and at other Boeing sites and collaborates with electronics groups across the company and around the world.

The engineer will lead and contribute to ASIC/FPGA design and verification from requirements capture and architecture through HDL implementation, physical design, simulation, prototyping, integration, and system validation. Depending on level and assignment, the role may lead multiple-design programs and engineering teams, manage execution against milestones, and train and mentor less senior engineers. The position is 100% onsite in Mountain View, California, and is designated for first shift. A U.S. Secret clearance is required post-start, and the candidate must be able to obtain one; U.S. citizenship is required for that clearance. The position also requires satisfying Boeing’s Conflict of Interest assessment and U.S. export-control requirements. Boeing does not sponsor employment visas.

Requirements

• Bachelor of Science degree in engineering (with a focus in electrical, mechanical, or aeronautical), computer science, data science, mathematics, physics, chemistry, or directly related non-U.S. equivalent qualifications.
• At least 10 years of ASIC/FPGA design or verification experience.
• Experience with ASIC/FPGA architectural definition, detailed design implementation, and functional verification using SystemVerilog, including delivery or release of production designs.
• Professional experience with hardware-based integration and testing of ASIC/FPGA designs.
• Ability to obtain a U.S. Security Clearance; U.S. citizenship is required for the clearance, and an interim and/or final U.S. Secret Clearance is required post-start.
• Must satisfy the Company’s Conflict of Interest assessment process.
• Must meet U.S. export-control compliance requirements as a U.S. Person.
• Senior level typical experience: 14 or more years of related work experience, or an equivalent combination of technical education and experience.
• Principal level typical experience: 20 or more years of related work experience, or an equivalent combination of technical education and experience.
• For Senior and Principal levels, education/experience is typically acquired through advanced technical education in a listed technical field; a bachelor’s degree is given as an example. ABET accreditation is preferred but not required in the United States.

Nice To Haves

• Master’s degree in electrical engineering, computer engineering/science, or a related field, or equivalent experience.
• Proven record of leading ASIC/FPGA design and/or verification teams, including tracking and reporting progress to stakeholders.
• Experience with hardware emulators, especially Palladium.
• Proficiency with hardware verification languages, including SystemVerilog and SystemVerilog Assertions.
• Ability to execute test plans.
• Proficiency in object-oriented programming concepts, including inheritance and polymorphism.
• Ability to create self-checking and reusable test benches from scratch.
• Experience developing functional coverage models and closing code coverage.
• Experience with high-speed SerDes interfaces such as JESD204C, PCIe, and Ethernet.
• Proficiency in scripting languages such as Make, Perl, and Python.
• Experience with revision-control systems such as SVN, CVS, and Git.
• Proficiency in Linux environments.
• Familiarity with space-based design techniques and radiation mitigation.
• Demonstrated history of first-pass success with ASIC designs.

Responsibilities

• Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams of design and verification engineers, and manage team execution to meet program milestones.
• Collaborate with customers, system engineers, and hardware engineers to capture requirements and architect digital logic functions for mission and customer needs.
• Evaluate ASIC/FPGA technology trade-offs and select parts by weighing schedule, cost, risk, area, and power against performance.
• Implement FPGA/ASIC designs using current practices and tools, from block-level microarchitecture and HDL coding through physical design realization, including gate-level netlists for ASIC designs.
• Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed.
• Perform static timing analysis, LEC, CDC, linting, and other checks to complete designs on schedule.
• Develop functional coverage models and perform code coverage to verify designs in simulation.
• Create self-checking, reusable test benches from scratch, applying object-oriented programming concepts and using UVM to create drivers, monitors, predictors, and scoreboards.
• Drive FPGA-based prototyping and validation according to program and system requirements and complexity.
• Validate designs through hardware integration testing with special test equipment, test beds, and higher-level systems as needed.
• Train and mentor less senior engineers and help build effective project teams.
• Conduct unit-level testing, verification, and validation of embedded software and firmware, using debugging tools such as oscilloscopes and logic analyzers to identify and resolve issues.
• Create and maintain requirements documents, design specifications, test plans, and interface control documents.
• Support integration of software and hardware components from initial hardware bring-up through final system validation.
• Analyze and improve system-resource efficiency, stability, scalability, and performance, often within low-power or memory constraints.

Benefits

• Eligible employees may enroll in health insurance, flexible spending accounts, health savings accounts, retirement savings plans, and life and disability insurance programs.
• Paid and unpaid time away from work.
• Competitive base pay and variable compensation opportunities.
• Relocation based on candidate eligibility; basic relocation is offered for eligible internal candidates.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior