About The Position

Collins Aerospace is seeking an experienced Principal Electrical or Computer Engineer to lead the design, implementation, and verification of advanced testbenches for high-performance digital ASICs and FPGAs. The position supports signal-processing and information-assurance technologies for Mission Systems programs as part of the Microelectronics Technology team. The role is onsite in Cedar Rapids, Iowa, and requires U.S. citizenship and an active existing DoD Secret clearance after the first day.

Requirements

  • Typically, a STEM degree and at least 8 years of relevant experience, or an advanced degree in a related field and at least 5 years of experience.
  • U.S. citizenship and the ability to obtain and maintain a U.S. government Secret security clearance; an active and existing clearance is required after day one.
  • Professional experience developing and simulating RTL designs using VHDL and/or Verilog in an FPGA or ASIC development environment.
  • Demonstrated ability to design, implement, and execute RTL-block verification testbenches using VHDL and/or SystemVerilog.
  • Working knowledge of chip-level verification methodologies, including constrained-random testing, functional coverage, and assertion-based verification using SystemVerilog.
  • Experience with revision control systems such as Git or Subversion to manage code, collaborate across engineering teams, and maintain configuration integrity.

Nice To Haves

  • Experience with ASIC/FPGA lab validation and debug using standard lab equipment.
  • Familiarity with DFT, manufacturability, and production test concepts.
  • Proficiency with Unix/Linux environments and scripting or software development using C, C++, Python, Perl, or shell.
  • Experience with industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
  • Strong written and verbal communication skills and the ability to work independently and collaboratively in fast-paced, multidisciplinary engineering environments.

Responsibilities

  • Architect and design verification environments using SystemVerilog with OVM/UVM.
  • Create written test plans and test cases, and track code and functional coverage.
  • Develop testbenches to verify RTL blocks using VHDL or SystemVerilog.
  • Recommend tools and practices to continually improve the group's ASIC/FPGA verification flow.
  • Contribute to engineering estimates for new program pursuits.
  • Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status.

Benefits

  • Medical, dental, and vision insurance.
  • Three weeks of vacation for newly hired employees.
  • 401(k) plan with employer matching and a separate employer retirement contribution, including a Lifetime Income Strategy option.
  • Tuition reimbursement program.
  • Student Loan Repayment Program.
  • Life insurance and disability coverage.
  • Optional pet, home and auto, additional life and accident, critical illness, group legal, and identity theft protection coverages.
  • Birth, adoption, and parental leave benefits.
  • Ovia Health, fertility, and family planning benefits.
  • Adoption Assistance.
  • Autism Benefit.
  • Employee Assistance Plan, including up to 10 free counseling sessions.
  • Healthy You Incentives wellness rewards program.
  • Doctor On Demand virtual doctor visits.
  • Bright Horizons child and elder care services.
  • Teladoc Medical Experts second-opinion program.
  • Potential eligibility for short- and long-term incentive compensation programs.
  • Potential eligibility for flexible spending accounts, flexible work schedules, paid time off, and holidays.
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