ASIC & FPGA Design Engineer
About The Position
This is a contracted position for a Sr. ASIC & FPGA Design Engineer. The role involves designing and developing digital ASICs and FPGAs, and/or mixed-signal ASICs. The engineer will implement designs using HDL (VHDL, Verilog, and/or SystemVerilog), develop verification methodologies and test benches, create and execute test plans, and conduct timing and noise analysis. The position also requires collaboration with cross-functional teams, support for lab integration and troubleshooting, and resolution of design issues related to timing and congestion. The role is 100% remote, with a potential for conversion to full-time employment requiring relocation to Southern California or Austin, TX. The pay rate is $100-$110/hr on W2.
Requirements
- 7+ years of experience in ASIC design and implementation
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
- Experience with FPGA & ASIC design
- Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
- Experience with Linux development environment
- Experience with design verification and test bench development
Nice To Haves
- Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
- Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
- Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs
- Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM)
- Strong object-oriented programming and scripting skills (Python, TCL, Perl)
- Experience with physical design flows and industry-standard EDA tools
- Experience with RTL2GDSII physical design and signoff flows
- Knowledge of deep sub-micron FinFET and CMOS technologies
- Experience with DFT/Scan/MBIST/LBIST methodologies
- Experience mentoring junior engineers
- Strong stakeholder management and communication skills
Responsibilities
- Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs
- Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog)
- Develop verification methodologies and test benches for block and system-level verification
- Create and execute test plans, develop test harnesses, and implement coverage models
- Conduct timing analysis, noise analysis, and other signoff checks
- Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
- Support lab integration and troubleshooting activities
- Resolve design issues and drive solutions for timing, congestion, and other implementation challenges
Benefits
- Comprehensive benefits package, subject to eligibility
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What This Job Offers
Career Level
Senior
