FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX•Irvine, CA

About The Position

SpaceX is developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures for the Starlink project. Starlink is the world's largest satellite constellation, providing fast and reliable internet globally. This role involves designing, building, testing, and operating satellites, consumer receivers, and the associated software. The engineer will work with cross-disciplinary teams to develop chips that enable connectivity in underserved areas, expanding the performance and capabilities of the Starlink network.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL.

Nice To Haves

ASIC/FPGA system integration experience.
Proficiency in Python, C/C++, and Bash.
Experience in designing DSP, digital communication system datapath blocks, and/or modem design.
Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
Experience and understanding of AXI/AHB/APB protocols.
Strong foundation in electrical engineering fundamentals.
Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers.
Ability to work in a dynamic environment with changing needs and requirements.
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
Demonstrated ability to work in a highly cross-functional role.
Enjoys being challenged and learning new skills.
Master’s in Electrical/Computer Engineering or related field.

Responsibilities

Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/System Verilog.
Optimize designs for power, performance, and area.
Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation.
Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab.
Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.
Collaborate with software engineers in developing production software for your designs.

Benefits

Comprehensive medical, vision, and dental coverage.
Access to a 401(k) retirement plan.
Short and long-term disability insurance.
Life insurance.
Paid parental leave.
Various other discounts and perks.
3 weeks of paid vacation.
10 or more paid holidays per year.
Paid sick leave.
Long-term incentives, in the form of company stock or long-term cash awards.
Potential discretionary bonuses.
Ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.