ASIC Design Verification Engineer, Machine Learning

Google•Sunnyvale, CA

7h•$138,000 - $197,000

About The Position

In this role, you’ll help shape AI/ML hardware acceleration by contributing to TPU technology used in demanding AI/ML applications. You’ll work on custom silicon solutions and verify complex digital designs, with a focus on TPU architecture and integration within AI/ML-driven systems. As part of a team developing ASICs that accelerate computation in data centers, you’ll take on responsibilities spanning project definition, design verification, and silicon bring-up. You’ll participate in the architecture, documentation, and verification of next-generation data center accelerators.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
At least 4 years of experience with design verification.
Experience with SystemVerilog or Verilog.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
At least 5 years of experience with industry-standard tools, languages, and methodologies relevant to developing silicon-based ICs and chips.
Experience contributing across the entire design and verification life cycle.
Experience verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
Familiarity with ASIC standard interfaces and memory system architecture.
Strong problem-solving, investigative, and communication skills, and the ability to work effectively in a team environment.

Responsibilities

Plan verification of complex digital design blocks by understanding design specifications and working with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry-leading formal tools.
Identify and write coverage measures for stimulus and corner cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and show progress toward tape-out.