ASIC Design Verification Engineer

BroadcomSan Jose, CA
1d

About The Position

We are looking for highly skilled and efficient Design Verification engineers that want to verify new designs that can evolve rapidly over the next several generations in a very dynamic market using industry proven constrained random methodologies with System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers working on PCIe and other host interfaces. The technology is constantly evolving and this provides a chance to work on leading edge technology that is also used in other product lines. This is a rare opportunity to be part of a successful product line. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Requirements

  • Self motivated personality with a strong presence to do things right.
  • Need to have a strong sense of teamwork and ability to work well with others.
  • Constrained random verification methodologies with experience driving completion via coverage closure.
  • Preferable to have skills with SV and UVM, well versed in OOP.
  • Experience with PCIe and experience with using 3rd party BFM is a strong plus.
  • Looking for candidates with a good understanding of datapath flows.
  • System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)
  • BSEE + 8+ years of related experience, or MSEE + 6+ years of experience
  • Be part of developing our next generation product in a series of high throughput Ethernet products that deliver unprecedented performance at critically important power efficiency.

Benefits

  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • company paid holidays
  • paid sick leave and vacation time
  • The company follows all applicable laws for Paid Family Leave and other leaves of absence.
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